oPath Summary:
Startpoint: Where the path begins (input port or flop clock pin).
Endpoint: Where the path ends (output port or flop data input pin).
Path Group:
Path Type: Setup, Hold, Recovery, Removal, Min Pulse Width, etc.
Slack:
Data Arrival Time Path: Details the delay contribution of each element along the data path:
Clock Network Delay (Launch): Latency from clock source to launch flop clock pin (relevant post-CTS).
Clock-to-Q Delay: Delay through the launch flop.
Logic Delay: Delay through each combinational cell (gate) on the path.
Net Delay: Delay through the interconnect wires connecting the cells (RC delay).
Incremental Delay & Path Delay: Cumulative delay at each stage.
Fanout – Load – Slew at each point (same to check in required time path )
Cell location – gives idea if cells are placed far away or not.
Data Required Time Path: Details the time budget available:
Clock Period: Target clock cycle time ( phase shift )
Clock Network Delay (Capture): Latency from clock source to capture flop clock pin (relevant post-CTS).
Clock Uncertainty: Skew + Jitter margins.
Library Setup/Hold Time: The intrinsic requirement of the capture flop.
CPPR/CRPR Adjustment: Pessimism removal credit applied (relevant in OCV modes post-CTS).
Cell/Net Details: Often shows input transition (slew), output capacitance (load), and specific delay values for each cell and net instance in the path.
- Analysis - What to Look For:
Magnitude of Slack: How large is the violation (negative slack) or margin (positive slack)?
Dominant Delay Components: Is the delay dominated by cell delay (logic complexity) or net delay (long wires, high capacitance)?
Number of Logic Levels: How deep is the combinational logic path? Very deep paths are inherently harder to time.
Cell Types: Are slow (HVT) cells used on a critical setup path? Are very fast (LVT) cells causing hold issues? Are there unusually slow/fast library cells?
Net Characteristics: Are there very long nets? Nets with high capacitance or slow transition times?
Clock Path Skew (Post-CTS): What is the skew between launch and capture clock paths? Is it helping or hurting the specific check (setup/hold)?
Constraints: Are the constraints applied to this path correct (clock period, I/O delays, exceptions)? Is it accidentally a false or multicycle path?
Pre-Route vs. Post-Route Analysis Differences:
Pre-route – estimated RC, usually optimistic. So if any Net gives high delay, needs careful consideration
Post route, we have actual RC delay, actual crosstalk impact as well and hence violations may increase.