How to improve timing QOR at CTS and post-CTS?

Q: "How to improve timing QOR at CTS and post-CTS?"

"oDuring CTS:\nOptimize Skew Groups: Define logical skew groups for paths to ensure they are balanced together. Use Non-Default Rules (NDRs): Apply NDRs to critical clock paths to use wider wires and greater spacing, reducing delay and crosstalk susceptibility. Clock Buffer Selection: Ensure the tool is using a good mix of clock buffers and inverters with less variation. Set clock targets appropriately like, skew, latency, DRC. Post-CTS: Run Post-CTS Optimization: Use commands like clock_opt …"

oDuring CTS:

Optimize Skew Groups: Define logical skew groups for paths to ensure they are balanced together.
Use Non-Default Rules (NDRs): Apply NDRs to critical clock paths to use wider wires and greater spacing, reducing delay and crosstalk susceptibility.
Clock Buffer Selection: Ensure the tool is using a good mix of clock buffers and inverters with less variation.
Set clock targets appropriately like, skew, latency, DRC.
Post-CTS:
Run Post-CTS Optimization: Use commands like clock_opt (ICC2) or ccopt_design (Innovus) which are specifically designed to fix timing violations after the clock tree is built.
Useful Skew:
Clock gate optimization.

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