o Register-to-Register (Reg2Reg): Starts at the clock pin of a launch flip-flop/latch and ends at the data input pin (e.g., D) of a capture flip-flop/latch. Both launch and capture elements are controlled by related clocks (often the same clock). This is the most common type of path analyzed for setup/hold within a synchronous design.
Input-to-Register (In2Reg): Starts at a primary input port of the design and ends at the data input pin of a sequential element. Constrained by set_input_delay.
Register-to-Output (Reg2Out): Starts at the clock pin of a sequential element and ends at a primary output port of the design. Constrained by set_output_delay.
Input-to-Output (In2Out or Pin-to-Pin Combinational): Starts at a primary input port and ends at a primary output port, passing only through combinational logic (no sequential elements). Often referred to as a “feedthrough” or “combo” path. Constrained by set_input_delay and set_output_delay relative to clocks, or sometimes by set_max_delay/set_min_delay directly between the ports.
Clock Gating Paths: Paths related to the setup/hold checks on the enable pin of clock gating cells.
User defined any groups. Reg2mem, mem2reg etc.
(Less Common) Data-to-Data Checks: Specific checks between data pins defined by constraints like set_data_check.