oDefining Modes: Different operating modes are : Functional mode - FUNC and test Modes: Scan Shift, Scan Capture, BIST
- Defined in MCMM setup with create_constraint_mode command and given separate SDC of each mode.
- Separate SDC Files: Each SDC file contains the appropriate set_case_analysis settings, relevant clock definitions (test clocks might differ from functional clocks), and potentially different timing exceptions or I/O delays specific to that mode.
- Mode-Specific Constraints within one SDC: Less commonly, complex logic within a single SDC file might be used to apply constraints conditionally, but separate SDCs or set_case_analysis are standard.
Checking Simultaneously (MMMC):
- Signoff: YES. Signoff STA must verify timing across all critical functional and test modes defined for the chip. tool runs analysis for numerous scenarios, each combining a specific mode (FUNC, TEST_SHIFT, TEST_CAPTURE, etc.) with a specific PVT and RC corner.
PnR: PnR typically focuses primarily on optimizing for the main FUNC mode(s).
Key TEST modes (like Scan Capture, if performance-limited by test clocks) might be enabled for timing analysis during PnR optimization (optDesign, route_opt), but often with lower optimization effort compared to FUNC mode.
Modes like Scan Shift, if run at a slow frequency, might only have basic checks run or might be deferred entirely to signoff STA, assuming the slow clock speed makes timing easy to meet.
The decision of which modes to actively optimize during PnR depends on project methodology, tool capabilities (MMMC PnR support), runtime constraints, and whether test modes are known to be timing-critical.