o We need to reduce cell delay or Net delay or use more skew – can use various methods for each.
o Reduce Cell Delay:
oCell Sizing (Upsizing): Increase drive strength of cells on the critical path. (Effective for small to moderate violations).
oVT Swapping (Lowering Vt): Swap cells to faster, lower-Vt variants (HVT->SVT->LVT). (Effective, but increases leakage).
oReduce amount of buffering if excessive bufs are added.
o Reduce Net Delay:
oBuffer Insertion: Insert buffers to break long nets or strengthen signals. (Good for net-delay dominated paths).
oReplace buffer with two inverters and reduce net length.
oAdjust cell position, keeping cell at middle of the net gives less net delay.
oRouting Optimization: Re-route critical nets on faster layers or using shorter paths. (Limited impact usually, but possible).
oUseful Skew: Delay the capture clock or speed up the launch clock path intentionally. (Requires careful analysis of side effects).
Fixing Different Violation Magnitudes:
- Small Violations (e.g., 5ps, 20ps): Often fixed by minor sizing changes (e.g., X2->X3), VT swaps on a few cells, or small useful skew adjustments.
- Moderate Violations (e.g., 300ps): May require more aggressive sizing (e.g., X1->X4), multiple VT swaps, buffer insertions, or significant useful skew. Logic restructuring might be needed. Placement is key.
- Large Violations (e.g., 500ps, 1ns): Indicate more fundamental issues. Simple sizing/VT swaps are unlikely to be sufficient. More likely constraint issues or missing MCP or pipelining.Fixing Setup/Hold: https://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html