oSDC Version: Specifies the SDC standard version used (e.g., set sdc_version 2.1).
Units: Defines units for time, capacitance, resistance, voltage, current, power (e.g., set_units -time ns …).
Clock Definitions:
create_clock: Defines primary clocks entering the design (at ports or internal pins), specifying their source, period, waveform (duty cycle, edge times).
create_generated_clock: Defines clocks generated internally (e.g., by PLLs, clock dividers/multipliers) based on a master clock.
set_clock_groups: Defines relationships between clocks (synchronous, asynchronous, exclusive).
set_clock_latency: Specifies source latency (external delay to clock definition point) and network latency (estimated or propagated internal delay).
set_clock_uncertainty: Defines margins for clock skew and jitter.
set_clock_transition: Specifies the desired transition time for clock nets.
Input/Output Delays:
set_input_delay: Specifies the arrival time of data at an input port relative to a clock edge. Represents the delay of the external logic driving the input.
set_output_delay: Specifies the required time for data at an output port relative to a clock edge. Represents the setup time requirement of the external logic receiving the output.
Timing Exceptions:
set_false_path: Identifies paths that should be ignored during timing analysis (logically impossible or irrelevant paths).
set_multicycle_path: Specifies paths that are allowed to take more than one clock cycle to propagate.
set_max_delay/set_min_delay: Overrides default setup/hold checks with specific delay requirements for certain paths.
Design Rule Constraints:
set_max_transition: Defines the maximum allowed signal transition time on nets or pins.
set_max_capacitance: Defines the maximum allowed capacitance load on output pins.
set_max_fanout: Defines the maximum number of gates an output pin can drive.
External Environment:
set_driving_cell: Models the drive strength of the external logic driving input ports.
set_load: Specifies the capacitive load connected to output ports.
Mode-Specific Constraints:
set_case_analysis: Sets specific pins/ports to constant values (‘0’ or ‘1’) to enable/disable logic for specific modes (e.g., functional vs. test).
Why Define I/O Delays?
Constrain Interface Paths: Primary inputs and outputs are startpoints and endpoints for timing paths. Without I/O delays, these paths are unconstrained, and the tool cannot optimize or verify the timing related to external interactions.