oReg2Reg WNS/TNS:
Acceptable: A small negative WNS (e.g., -50ps to -200ps for a multi-GHz design, perhaps -10% to -20% of the clock period) might be considered acceptable as a starting point for PnR. TNS should ideally be manageable.
Context: The acceptable value depends on how much improvement is expected from PnR optimizations (better placement, buffering, useful skew, more accurate parasitics).
- Extremely High Negative WNS/TNS: If the WNS is very large negative (e.g., approaching or exceeding the clock period) or TNS is enormous:
Unrealistic Constraints: Clock frequency target is too high for the technology/architecture. SDC constraints (I/O delays, exceptions) might be incorrect or too tight.
Poor RTL Quality: Inefficient logic structure, very long combinational paths, complex computations within a single cycle.
Incorrect Libraries: Using the wrong speed/Vt libraries for synthesis.
Synthesis Tool Issues: Incorrect settings, poor optimization effort.
Action: The issue must be investigated and addressed in synthesis (fixing constraints, guiding the tool, requesting RTL changes)
- ICG WNS (Integrated Clock Gating):
Target: ICG setup timing (WNS) should ideally be positive or very close to zero after synthesis. Clock gating checks are often harder to fix post-synthesis compared to regular reg-to-reg paths.
Negative ICG WNS: If ICG setup WNS is significantly negative, it’s a concern. It implies the enable logic path is too slow. This should be prioritized for fixing during synthesis, potentially by:
Optimizing the enable logic path.
Adjusting clock gating insertion strategy.
Using faster cells for the enable logic or the ICG cell itself.