Cell Sizing / (Downsizing): Replace cells on non-critical timing paths with smaller drive-strength variants (e.g., X4 -> X2 -> X1).
Removing unnecessary buf/inverters: If added on short nets, may not be really required and can be deleted.
Leakage Optimization Modes: PnR/Optimization tools often have specific modes or commands (setOptMode -powerEffort high, optimize_power)
Clock Gating Enhancement: While primarily done during synthesis/CTS, post-route optimization might identify further opportunities for clock gating refinements or sizing of clock gating cells themselves, assuming it doesn’t impact timing.
Multi-Bit Cell Merging: Replacing multiple single-bit flops/latches with equivalent multi-bit cells can sometimes reduce overall leakage and dynamic power, although this is more of a synthesis/placement strategy than a post-route recovery technique.