How do you instruct your tools to resolve post-clock violations? What role does “useful skew” play in these scenarios?

oEnable Post-CTS/Post-Route Optimization:

  • Innovus: optDesign -postCTS (after CTS), optDesign -postRoute (after routing). These commands invoke timing-driven optimization engines.
  • ICC2: clock_opt -stage cts_optimize (after CTS build), route_opt (performs routing and optimization iteratively).
  • Specify Effort Levels: Increase the optimization effort.
  • Innovus: setOptMode -effort high|extreme
  • ICC2: Options within place_opt, clock_opt, route_opt to control effort (e.g., -effort high).
  • SI-Aware Optimization: Ensure Signal Integrity (crosstalk) aware optimization is enabled if SI violations are contributing to timing issues.
  • Innovus: setOptMode -crosstalkAware true
  • ICC2: set_si_options -delta_delay true -glitch true; route_opt -xtalk_driven
  • Role of “Useful Skew”:

Setup Violation Fixing:

If a path is failing setup, the tool might intentionally delay the capture clock path or speed up the launch clock path. Increasing the skew to help setup.

Hold Violation Fixing:

If a path is failing hold, the tool might intentionally delay the launch clock path or speed up the capture clock path effectively increasing hold slack.

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