oClean Sanity Checks: The netlist must pass all critical sanity checks:
No fatal errors in check_design / check_netlist (no multi-driven nets, no floating inputs on critical paths, correct connectivity).
No unresolved references (check_library passes, all cells have lib/lef).
No critical errors in check_timing (all clocks defined, critical paths constrained, no unconstrained registers intended to be clocked). Minor unconstrained paths might be acceptable if understood and deemed non-critical or intended false paths.
- Timing QOR:
Reasonable WNS/TNS: The Worst Negative Slack (WNS) and Total Negative Slack (TNS) reported by synthesis STA should be within acceptable limits for the target clock frequency. Very large negative slack (e.g., >> 1 clock cycle) might indicate fundamental issues (unrealistic constraints, poor RTL, wrong target library) that PnR cannot fix. Small negative slack (-10% to -20% of the clock period, depending on the design/node) is often acceptable, as PnR tools have more powerful optimization engines and accurate parasitic information.
No Excessive DRV Violations: While PnR primarily fixes DRVs (Design Rule Violations like max_transition, max_capacitance), the number and severity reported by synthesis should not be excessively high, as this might indicate poor library choices or constraint issues.
- Area QOR: The synthesized cell area should be reasonably close to initial estimates or targets. A massively larger-than-expected area might indicate synthesis issues or unrealistic constraints.
- LEC Clean:
Power QOR (If applicable): If power analysis was run during synthesis, the estimated static and dynamic power should be within acceptable bounds.