Cell Sizing, VT Swap to allowed VT at placement, Buffer insertion, Logic optimization, These optimizations are typically performed automatically by the place_opt / optDesign -preCTS commands based on the timing constraints (SDC) and available libraries and don’t use settings.
- Need manual observation of critical paths,
- high fanout: it can cause trouble in closing timing as balancing CTS and placing all FFs properly will be difficult for the tool.
- Cells are spread for longer distance: check the connectivity of start point endpoint, analyse module connection and give appropriate bound or region.
- Macro placement analysis and fanin fanout checks gives better idea.