oMin Pulse Width (MPW) Violation: A timing check ensuring that the duration of a clock pulse (either the high phase or the low phase) at the clock pin of a sequential element (or other sensitive pins like asynchronous resets) is sufficiently long for the cell to function correctly. Libraries specify min_pulse_width_high and min_pulse_width_low requirements. A violation occurs if the actual pulse width reaching the pin is shorter than the required minimum.

oset_case_analysis: particular port or pin in the design should be treated as having a constant logic value (0 or 1) for the duration of the timing analysis run (or for specific modes).

Purpose:

Mode Setting: To model different operating modes of the chip (e.g., functional mode vs. test mode) where certain control signals are tied high or low.

Disabling Logic: By setting control signals (like multiplexer selects, enables) to constant values, specific logic paths can be disabled for timing analysis,

oFalse Path (set_false_path):

Specific path between a startpoint and endpoint cannot be logically sensitized during normal circuit operation. Although a physical path exists, signals will never actually propagate from the startpoint to the endpoint along that path under functional conditions

STA Action: The tool completely ignores this path for all timing analysis (setup, hold, DRCs). It assumes the path has infinite time to propagate.

When to Use: Only for paths that are guaranteed to be functionally impossible or irrelevant to the timing modes being analyzed.

o **Routing (**routeDesign or similar): This stage focuses on physically connecting the pins of all standard cells and macros. goal is connectivity and DRC correctness.

Sub-stages: Often involves Global Routing (planning paths through routing regions/GCells), Track Assignment (assigning nets to specific tracks), and Detail Routing (drawing the exact wires and vias, ensuring DRC rules like spacing/width are met).

Timing/Optimization: Basic timing considerations might influence routing choices (e.g., prioritizing critical nets), but large-scale timing optimization (like cell sizing, buffer insertion) is not the primary focus. The main goal is to achieve a DRC-clean, fully routed design.

oDRV – Setup -Hold

• Fixing DEV first can help reduce setup violations as well.
• Usually fix setup first as fixing setup requires touching many cells across timing path. Swapping and sizing on full path based on slack number. This can impact hold violations.
• For hold fix, usually we fix at endpoint, insert buffer or create long route. Touching endpoint has less to no impact on setup hence hold is fixed at last.

oMismatch with Layout: An outdated SPEF reflects an older version of the layout. If placement or routing has changed since the SPEF was generated, the RC values in the SPEF will not accurately represent the current physical structure. Wire lengths, adjacencies (coupling capacitance), and via counts will be wrong.

• Mismatch with Process/Library: If the RC corner data itself is outdated (e.g., from a previous PDK version or library characterization), the fundamental R-per-square or C-per-unit-length values used for extraction might be incorrect for the current process target, even if the layout is current.

For ex, if earlier net was longer and hence in old spef, RC is more. Now latest db, net is short, RC is less but using old spef hence timing calculation will be pessimistic and vice versa.