oA “cell cannot be legalized” error during an ECO (especially a hold ECO, which often involves adding buffers) means the PnR tool cannot find a valid, DRC-clean placement location for the newly added or modified cells that aligns with the site rows and doesn’t overlap with other cells.

High Cell Density/Congestion: There’s simply no physical space (empty sites) to place the new buffer without causing overlaps.

Filler cells not removed from the design.

Yes, it is possible and quite common to see negative setup and hold times specified in standard cell timing libraries (.lib).

There are internal delays along the clock path and data path within the cell, from the input pins to the internal latch.

Negative Setup: If the internal clock path delay is significantly longer than the internal data path delay plus the internal latch’s intrinsic setup time, the data pin (D) can actually change after the active clock edge at the clock pin (CK) and still be captured correctly.

o Static Power: Power consumed when the circuit is powered ON but not actively switching. It’s primarily due to leakage currents flowing through transistors that are supposed to be OFF.

Main Components: Subthreshold leakage, gate leakage, junction leakage.

Factors: Increases significantly with lower threshold voltages (Vt) and at smaller technology nodes. Also increases with temperature.

Dynamic Power: Power consumed during the switching of logic states (when signals transition between ‘0’ and ‘1’).

oCMOS stands for Complementary Metal-Oxide-Semiconductor. It’s the dominant technology for constructing integrated circuits.

oComplementary: It uses both NMOS (N-channel Metal-Oxide-Semiconductor) and PMOS (P-channel Metal-Oxide-Semiconductor) transistors, typically paired together.

oStructure:

o**NMOS:** Conducts current (electrons) when its gate voltage is high (logic '1').  Built on a P\-type substrate.

o**PMOS:** Conducts current (holes) when its gate voltage is low (logic '0'). Built on an N\-type substrate (or N\-well).

oBasic Inverter: The fundamental CMOS gate is the inverter. It consists of one PMOS transistor connecting the output to VDD (power supply) and one NMOS transistor connecting the output to VSS (ground).

o Decap Cells (Decoupling Capacitors): These are essentially capacitors (often MOSCAPs) placed near switching logic.

Need: to supply instantaneous current demands during fast switching events, stabilizing the power supply voltage (VDD/VSS) and mitigating dynamic IR drop and voltage noise on the power grid

Filler Cells: These cells fill the empty spaces left in standard cell rows after placement and optimization. They typically only contain VDD/VSS connections and substrate/well contacts.

Need: Ensure N-well and substrate continuity for proper biasing. Provide continuous power rail connections along the rows. Required for manufacturability (uniform density for CMP - Chemical Mechanical Polishing).

o Creating a Voltage Area (Physical Implementation): A voltage area is a physical region on the chip floorplan designated to contain logic operating at a specific voltage level different from other regions, or logic that can be power-gated:

Define the physical boundary (coordinates) of the region- create_voltage_area

Associate this region with a specific power domain defined in the UPF/CPF.

cells belonging to the corresponding power domain are placed within this physical voltage area during placement.