o DRC (Design Rule Check): checks if the physical layout is as per foundry rules, ensure it can be manufactured reliably with acceptable yield.

Types of Rules: Include minimum width, minimum spacing (intra-layer and inter-layer), minimum area, via enclosure, overlap requirements, antenna rules (often checked separately but fundamentally DRCs), density rules, and many complex conditional rules (e.g., end-of-line spacing, notch spacing).

Fixing DRCs:

Spacing Violations: Increase the space between the violating shapes (e.g., move wires further apart).

o Electromigration (EM): The gradual displacement and migration of metal atoms in an interconnect (wire or via) caused by the momentum transfer from flowing electrons. Over time, at high current densities and temperatures, this movement can lead to:

Voids: Depletion of metal atoms in a region, increasing resistance and potentially causing an open circuit (wire break).

Hillocks: Accumulation of metal atoms in another region, potentially causing shorts to adjacent wires.

oFunctional ECO: An Engineering Change Order implemented to fix a logical bug in the design’s functionality or to add/modify a feature. The change originates from an RTL modification.

• RTL code is modified to fix the bug or add the feature.
• The changed RTL is synthesized (often just the affected module).
• Synopsys Formality ECO, Cadence Conformal ECO compares the original synthesized netlist (the one in PnR) with the newly synthesized netlist from the changed RTL.
• The ECO tool identifies the logical differences and generates a set of gate-level changes (ECO patch – add/delete/modify gates and connections) needed to transform the PnR netlist to match the new functionality. This patch is often a sequence of tool commands (add_cell, remove_cell, connect_net, disconnect_net, etc.).

Implementation in PnR: The ECO patch (script) is applied to the PnR database, followed by incremental placement (legalization) and routing of the modified logic.

·For power analysis, each cell’s power dissipation has been characterized in the library (.lib) file. For leakage power, the EDA tool simply adds up the leakage power of each cell. (Note: Leakage power is usually state dependent) For dynamic power, the EDA tool either estimates net capacitance before P&R or calculates net capacitance after P&R. The designer has to provide the toggle rate. This can be based on educated guess, experience, simulation, or emulation.

oLVS (Layout Versus Schematic): A critical physical verification process that compares the electrical circuit extracted from the physical layout database (e.g., GDSII, OASIS) against the intended circuit described by the source schematic netlist (e.g., SPICE or Verilog netlist).

• Inputs:
• Layout Database: The physical layout design file (GDSII, OASIS)
• Source Netlist: The “golden” netlist representing the intended circuit schematic (e.g., SPICE netlist for custom designs, Verilog netlist for digital designs).
• Rule Deck: Provided by the foundry, this file tells the LVS tool how to identify devices (transistors, resistors, capacitors, diodes) from the layout layers, how to determine connectivity, and how to extract parameters (like W/L for transistors).
• Configuration/Setup Files: Files to control the LVS run, specify top cells, map power/ground names, define device properties to compare, set tolerances, etc.
• Schematic View vs. Layout View (in LVS context):

Schematic View: Circuit from Golden netlist.

o Traditional Corners (Simplified View - often just called C corners initially): Used for short nets where resistance can be ignored or very less.

Cworst (Maximum Capacitance, Cmax): Models process variations that maximize interconnect capacitance (e.g., wider wires, thicker metal, smaller spacing, higher dielectric constant). Often assumes minimum resistance for these conditions (though not always explicitly linked). Used primarily for setup timing analysis (longest path delay).

Cbest (Minimum Capacitance, Cmin): Models process variations that minimize interconnect capacitance (e.g., narrower wires, thinner metal, larger spacing, lower dielectric constant). Often assumes maximum resistance. Used primarily for hold timing analysis (shortest path delay).