o Fixing IR drop involves 1) strengthening the Power Distribution Network (PDN) to reduce its resistance or 2) reducing the current drawn by the logic.

• During Placement/Floorplan (Preventative)
• Robust PDN Design: Plan a dense power grid using wide straps/rings on low-resistance metal layers with ample vias
• Macro Placement: Place high-power macros near power sources or ensure they have strong connections to the power grid.
• Cell Placement: Avoid clustering high-power or high-switching activity cells in one area. Use density controls.
• During Post-Route Optimization / ECO Stage:
• Strengthen PDN:
• Add/Widen Power Straps: Introduce more power/ground stripes in areas with high voltage drop or increase the width of existing straps.
• Add Power Vias: Increase the number of vias connecting different layers of the power grid, at connections to cell rails, to reduce vertical resistance.
• Add Decap Cells (Primarily for Dynamic IR):
• Reduce Current Draw:
• Cell Downsizing: Replace high-power cells in the violating region with smaller drive-strength equivalents, if no timing violations.
• VT Swapping (Higher Vt): Swap cells to higher-Vt to reduce leakage current (helps static IR) and slightly reduce peak dynamic current (helps dynamic IR), If no timing issues.
• Spread High-Activity Cells: If dynamic IR drop is caused by simultaneously switching cells clustered together, try spreading these cells apart during ECO placement

oIt requires careful analysis and is typically done for critical paths where there is no scope in data path.

• For setup:
• Early the launch clock or delay the capture clock so skew can be increased which helps in setup violation. With this you are reducing the skew in path before and after this path. So there should be setup margin in both adjacent paths and hold margin in same path.
• For Hold:
• Delay the launch clock or early the capture clock so skew can be reduced which helps in hold violations. Path should have setup margin. And path before and after this path should have hold margin as for them it will increase the skew.
• Analyze Clock Path:
• Trace the launch and capture clock paths for the violating timing path.
• Identify existing buffers/inverters on these clock paths, their drive strengths, and locations.
• Understand the common clock path and the diverging points.
• Make desired changes after diverging point, ex, upsize, downsize, add delay based on setup or hold fix.
• Apply ECO in PNR tool and run STA to verify fixes

oIn a low-power project with specific operating performance points (OPPs) like:

• “low_svs” (Low Standard Voltage Swing, likely a power-saving mode)
• “turbo” (a high-performance mode, likely at a higher voltage),

Setup Analysis:

low_svs Mode: Analyze setup at the slowest process corner (SS/SSG) combined with VddL and worst-case temperature (often high temp for CMOS). This is SSG_VddL_HighTemp_RCworst. This represents the slowest the logic will be in low power mode.

turbo Mode: Analyze setup at the slowest process corner (SS/SSG) combined with VddH and worst-case temperature. This is SSG_VddH_HighTemp_RCworst. This is the absolute performance bottleneck.

o Vector-based Analysis: Used VCD (Value Change Dump) or FSDB files generated from gate-level simulations of specific, high-activity scenarios (e.g., boot-up sequence, high-performance benchmark execution, specific test modes). These vectors provide accurate, cycle-by-cycle switching activity for those specific scenarios, allowing us to identify peak IR drop and EM stress under known critical operating conditions

• Vectorless Analysis: To ensure broader coverage and identify potential worst-case scenarios not easily captured by specific VCDs, used vectorless dynamic analysis.
• Usually Vectorless is often used earlier in the flow for faster feedback, while vector-based analysis with critical scenarios mandatory for final signoff
• Given Toggle Rate? à Yes, toggle rates were used, primarily for:
• Static IR Drop/Power Analysis: Average toggle rates (often derived from synthesis estimates, statistical propagation, or averaged from simulations) used along with leakage data to calculate the average current for static analysis.
• Vectorless Dynamic Analysis (Seeding): Some vectorless techniques might use initial toggle rate information as a starting point for activity propagation or statistical analysis.
• Given TWF file? Yes, TWF (Timing Window File) files were used as input for dynamic analysis, especially for vectorless methods
• A TWF file contains information about the possible switching time windows for signals in the design.
• For each net or pin, it specifies the earliest and latest possible time (relative to the clock edge) that a signal transition (rise or fall) can occur

oDRC (Design Rule Check): Verifies that the layout geometry adheres to the manufacturing constraints (design rules) specified by the foundry for the target technology node. This includes checks for minimum width, spacing, area, enclosure, overlap, etc., for all layers (metal, poly, diffusion, vias, etc.). Ensures the layout can be physically manufactured with acceptable yield.

LVS (Layout Versus Schematic): Compares GDS(Layout) vs schematic(Netlist). It verifies that the layout correctly implements the intended logic in netlist. It checks, device types, and device parameters (like transistor W/L). Checks for shorts, opens, incorrect connections, missing/extra devices, and parameter mismatches.

o Antenna Effect (Plasma-Induced Gate Oxide Damage): During semiconductor manufacturing, plasma etching processes are used to remove material. In these processes, charged particles (ions, electrons) bombard the wafer surface. If a long metal wire (acting like an “antenna”) connected only to a transistor gate is exposed during etching, it can accumulate significant charge from the plasma. If this charge builds up enough voltage, it can exceed the breakdown voltage of the thin gate oxide layer beneath the transistor gate, causing damage (latent defects or immediate breakdown). This damage can lead to reliability issues or functional failure. The risk increases with the Increase in metal area compared to gate area. Which is called antenna ration.