o Setting Limits: setUsefulSkewMode -maxAllowedDelay <Value>

Checks Needed When Applying Useful Skew: when usefulSkew is enabled in preCTS and at CTS, tool does all the checks before applying for the skew. At ECO if doing manual adjustment, below things to be checked:

• Hold Time on the Same Path: The most critical check.
• Timing to Launch Flop: Check setup and hold timing for paths ending at the launch flop. If skew is borrowed from this path, it may get setup violation.
• Timing from Capture Flop: Check setup and hold timing for paths starting from the capture flop. If skew borrowed from this path, it may get setup vio.
• Overall QOR: After applying useful skew (usually as part of an optimization run or ECO), re-run full STA to ensure no new violations have been created
• CPPR Impact: Pushing Capture or pulling Launch flop to add skew, may change your CPPR and contribute to timing violations.

o Clock Latency (Insertion Delay): The time it takes for the clock signal to propagate from its source (the point where the clock is defined, e.g., a primary input port) to the clock pin of a specific sequential element (sink pin, e.g., a flip-flop’s CK pin).

Source Latency: Delay from the actual clock origin (e.g., crystal oscillator) to the clock definition point in the design (defined using set_clock_latency -source). This models external delay.

o Clock Skew: The difference in arrival time of the clock at capture FF and launch FF.

Local Skew: Skew between two specific, related flops (e.g., launch and capture flop of a timing path).

Global Skew: The difference between the maximum and minimum clock latency across all sinks in a domain.

Causes of Skew:

Different Path Lengths: The physical distance (wire length) from the clock root to different sinks varies due to their placement locations.

o Increased Power Consumption: Longer clock trees generally contain more buffers/inverters and longer nets. This leads to higher power consumption.

Increased Area: More buffers/inverters consume more silicon area.

CPPR and OCV Impact: longer tree not properly balanced or may not have more common path. Reducing CRPR effect. More cells means more OCV impact and delay variation causing timing closure difficult

Increased Jitter Accumulation: Longer paths with more buffers can potentially accumulate more jitter, increasing clock uncertainty and further tightening timing constraints.

o Useful Skew: The deliberate introduction of a controlled amount of clock skew between specific launch and capture flops to help meet timing requirements (either setup or hold). Instead of minimizing skew everywhere (the default CTS goal), useful skew leverages available timing margin from one path to fix a violation on another.

Fixing Setup with Useful Skew:

Equation: Setup Slack ≈ (Clock Period + Skew) - Data Path Delay - Uncertainty - Lib Setup. Increasing positive skew directly increases setup slack.

oIf you place ICG near to source, dynamic power consumption will reduce. This is because most of the clock buffers are in fanout of clock gater. These clock buffers will not toggle when clock gating is enabled.

• But placing ICG near to source increases the uncommon paths. These uncommon paths can behave differently, so during STA these need to be taken into account that extra uncertainty.
• If you place ICG near to sink, most of the clock buffers are in common path. It is easy to met timing compared to scenario-1.
• But at the same time dynamic power consumption is increased.
• Remember, there is trade-off between power and timing.
• Ideally, Integrated Clock Gating (ICG) cells should be placed physically close to the group of flip-flops (sinks) they are gating.

Improve CTS Balancing: CTS tools balance delay up to the inputs of the ICG cells. Placing the ICG close to the sinks means the final, unbuffered gated clock segment is short and contributes less variable delay, making overall skew balancing more predictable.