o Signal Integrity (SI): Quality of an electrical signal as it travels from a driver to a receiver through an interconnect. Major SI concerns include:

o Crosstalk: Unwanted coupling between adjacent signal nets.

o IR Drop: Voltage drop on the power/ground network affecting cell performance.

o Electromigration (EM): Reliability issue due to metal migration under high current density.

o Timing Jitter/Phase Noise: Variations in the timing of signal edges, especially critical for clocks.

The selection involves a trade-off between PnR runtime/effort and signoff accuracy/coverage.

Signoff: Aims for comprehensive coverage of all conditions the chip might experience. It typically includes:

Multiple PVT Corners: Extremes of Process (SS, FF, SF, FS), Voltage (min, max), and Temperature (min, max), plus typical (TT).

Multiple RC Corners: Worst/Best RC combinations (RCworst, RCbest, Cworst, Cbest, potentially crosstalk corners).

Multiple Modes: Functional modes, test modes (Scan Shift, Scan Capture, BIST), potentially low-power modes.

1. Increase Spacing: Physically increase the distance between the victim and aggressor nets during routing. This directly reduces coupling capacitance (Cc​). (Most effective but consumes routing area).

Shielding: Insert a static net (tied to VDD or VSS) between the victim and aggressor. The shield net intercepts coupling capacitance, preventing interference. This can add coupling cap on signal net causing delay.

Layer Change: Route the victim or aggressor on different metal layers for a portion of their length to reduce parallel run length and coupling.

o Handling Static IR Drop: Static IR drop is primarily due to the resistance of the power grid (Vdrop​=Iavg​×Rgrid​). If you cannot improve Rgrid​ (by widening straps/adding vias):

• Reduce Average Current (Iavg​):

Downsize Non-Critical Cells: Replace cells contributing significantly to static leakage in the affected region with smaller drive-strength variants (if timing permits).

VT Swapping (High VT): Swap cells to higher Vt variants (LVT -> SVT -> HVT) in the affected area. Higher Vt cells have significantly lower leakage current. This requires available timing slack.

oEnable Post-CTS/Post-Route Optimization:

• Innovus: optDesign -postCTS (after CTS), optDesign -postRoute (after routing). These commands invoke timing-driven optimization engines.
• ICC2: clock_opt -stage cts_optimize (after CTS build), route_opt (performs routing and optimization iteratively).
• Specify Effort Levels: Increase the optimization effort.
• Innovus: setOptMode -effort high|extreme
• ICC2: Options within place_opt, clock_opt, route_opt to control effort (e.g., -effort high).
• SI-Aware Optimization: Ensure Signal Integrity (crosstalk) aware optimization is enabled if SI violations are contributing to timing issues.
• Innovus: setOptMode -crosstalkAware true
• ICC2: set_si_options -delta_delay true -glitch true; route_opt -xtalk_driven
• Role of “Useful Skew”:

Setup Violation Fixing:

oIncorrect Nets / Connectivity Errors: This section details discrepancies in how nets are connected.

Shorts: When Schematic has more nets but layout has less nets, layout has short.

Opens: A single net in the schematic corresponds to two or more unconnected nets in the layout.

Incorrect Instances / Devices: Discrepancies in the number or type of devices.

Missing Devices: A device present in the schematic is not found in the corresponding location/netlist in the layout.