oIf setup and hold both are critical on same path, check if it is exact same path or if there is any diversion from combo logic in setup and hold timing path.

If there is any diversion, add delay at that point so hold can be fixed without touching setup critical path.

• If timing path is exactly same and having setup and hold violations, there could be two reasons,
• Crosstalk impact – crosstalk will add delay in setup and reduce it in hold. Impacting adversely both setup and hold. Fixing crosstalk should give margin to fix setup and hold.
• If there is no crosstalk, there can be very high setup and hold time requirement from endpoint. (may happen with reg2mem paths)
• Check if such cells can be replaced with less access time cell.
• To get margin in setup and hold both, you need to use cell with less delay variation across SS-FF corners.
• Use LVT cells in data path instead of SVT/HVT. Use low drive strength cells and reduce net legth so that OCV impact can be reduced giving margin for setup and hold.

o Register-to-Register (Reg2Reg): Starts at the clock pin of a launch flip-flop/latch and ends at the data input pin (e.g., D) of a capture flip-flop/latch. Both launch and capture elements are controlled by related clocks (often the same clock). This is the most common type of path analyzed for setup/hold within a synchronous design.

Input-to-Register (In2Reg): Starts at a primary input port of the design and ends at the data input pin of a sequential element. Constrained by set_input_delay.

o Via Pillar: A structure used in advanced process nodes (like FinFET nodes) to create a lower-resistance vertical connection between metal layers compared to traditional single vias or via arrays. It typically consists of:

Stacked, short metal segments (“fingers”) on intermediate metal layers, aligned vertically.

These segments are connected by vias above and below, essentially forming a “pillar” of alternating via and short metal bar segments running vertically through multiple layers.

oOCV analysis (like AOCV/POCV or simple derating) applies different delay values for ’early’ (fast) and ’late’ (slow) conditions.

For a setup check, the launch clock path uses late delays, and the capture clock path uses early delays. For a hold check, it’s reversed.

However, both clock paths often share a common segment starting from the clock root before diverging. Applying both early and late derates simultaneously to this same physical common path introduces artificial pessimism because the common path cannot physically be both fast and slow at the exact same instant.

oMin Pulse Width (MPW) Violation: A timing check ensuring that the duration of a clock pulse (either the high phase or the low phase) at the clock pin of a sequential element (or other sensitive pins like asynchronous resets) is sufficiently long for the cell to function correctly. Libraries specify min_pulse_width_high and min_pulse_width_low requirements. A violation occurs if the actual pulse width reaching the pin is shorter than the required minimum.

oFalse Path (set_false_path):

Specific path between a startpoint and endpoint cannot be logically sensitized during normal circuit operation. Although a physical path exists, signals will never actually propagate from the startpoint to the endpoint along that path under functional conditions

STA Action: The tool completely ignores this path for all timing analysis (setup, hold, DRCs). It assumes the path has infinite time to propagate.

When to Use: Only for paths that are guaranteed to be functionally impossible or irrelevant to the timing modes being analyzed.