Area and Utilization: within limit.

Macro Placement Legality: Ensure all macros are placed legally (not overlapping) and are aligned to the site grid.

Pin Placement: Check that all I/O pins are placed and that their locations are reasonable for top-level connectivity.

Early IR Drop Analysis: A static IR drop analysis is run on the power distribution network (PDN) to check for significant voltage drops. This helps validate that the power grid structure (straps, rails, and vias) is robust enough.

o Max Transition (or Max Slew): This is a design rule constraint specified in the library (.lib) that defines the longest permissible time for a signal to transition from one logic level to another (e.g., 10% to 90% of Vdd).

Purpose: Ensures signal integrity and predictable cell behavior. Slow transitions can cause:

Increased sensitivity to noise (crosstalk).

Increased short-circuit power consumption within the receiving cell.

Unreliable timing (cell delays are characterized based on input slew; very slow slews might fall outside characterization).

o Variability Management: Use advanced modeling (AOCV/POCV) and variation-aware design techniques. Statistical timing and yield analysis become crucial.

o Complex Design Rules: multi-patterning rules (coloring, masks), pitch restrictions, via rules, and DFM (Design for Manufacturability) requirements like dummy fill, via ladders, etc.

o Power Integrity: Aggressive power grid design (dense mesh), extensive use of decap cells, careful IR drop and EM analysis (static and dynamic) are mandatory. Lower voltage margins make designs very sensitive.

Delay is due to cell and interconnect. When area is congested, when tool calculates timing, it may consider detour routes, adding more delay.

When cells are spreaded just enough to solve congestion, it may reduce route length as well, helping in congestion and timing both.

Instead of broad spreading, use more localized techniques: Apply partial blockages with lower blockage percentages (e.g., 10%) only in the absolute peak congestion GCells, rather than large areas.

oSDC Version: Specifies the SDC standard version used (e.g., set sdc_version 2.1).

Units: Defines units for time, capacitance, resistance, voltage, current, power (e.g., set_units -time ns …).

Clock Definitions:

create_clock: Defines primary clocks entering the design (at ports or internal pins), specifying their source, period, waveform (duty cycle, edge times).

create_generated_clock: Defines clocks generated internally (e.g., by PLLs, clock dividers/multipliers) based on a master clock.

set_clock_groups: Defines relationships between clocks (synchronous, asynchronous, exclusive).

o Technology LEF (tech.lef): Defines the process technology rules and properties. It contains information common to the entire chip manufacturing process, independent of specific standard cells.

Content:

Layers: Defines all routing (metal), cut (via), masterslice (poly, diffusion), and other layers used in the technology. Includes name, type, direction preference, pitch, width, spacing rules (DRCs), resistance, capacitance per unit area/length, thickness, color (for multi-patterning).

Vias: Defines standard via types connecting different layers, including their cut patterns, enclosure rules, and resistance.