oPlacement Legality: check for Overlaps: Verify that no standard cells overlap each other (checkPlace, checkLegality). All cells must occupy legal sites defined by the floorplan rows.

Congestion Analysis:

Global Congestion Map:

Density Checks:

Timing Analysis (Pre-CTS):

Setup Timing: the violations should be reasonable and manageable for subsequent optimization stages. Acceptable violation depends on what kind of cells used, whether LVT enabled or not at place, what is extra uncertainty given etc.

• 7nm Fab Challenges: https://semiengineering.com/7nm-fab-challenges/
• Signoff Challenges at Advanced Nodes: https://www.einfochips.com/blog/sign-off-the-chip-asic-design-challenges-and-solutions-at-cutting-edge-technology/

o Placement blockage of type “Hard” means that placeDesign will not place any cells in this area. Use this blockage type to totally restrict standard cells from being placed here.

A placement blockage of type “Soft” means that placeDesign will not place any cells in this region. However, placement legalization, timing optimization, and clock tree synthesis (CTS) can place buffers/inverters in this area. This blockage type is often used to block channels between macros. It prevents the placer from placing standard cells in this area, thus avoiding congestion problems. However, optimization is allowed to insert buffers/inverters in these channels, which is useful when buffering long nets and can improve timing and routability.

• Gate-Level Netlist:
• Timing Libraries (.lib or .db**)**
• Physical Libraries (.lef**):**
• technology process rules (tech LEF).
• Timing Constraints (SDC - Synopsys Design Constraints):
• Power Intent (UPF/CPF - Optional but common):
• RC Extraction Files (Optional initial estimate, more critical later): tlu+, qrcTech
• Floorplan Definition File (DEF - Optional):
• Scan Definition File (Scan DEF - Optional):
• MMMC (Multi-Mode Multi-Corner) Setup File

o Inaccurate Wire Load Models (WLMs) in Synthesis: Synthesis often uses statistical WLMs to estimate interconnect delay, which can be highly inaccurate compared to the actual delays based on physical placement.

Large Distance: Macros or blocks that communicate frequently are placed too far apart, leading to long interconnect delays.

Congestion: High placement congestion forces routing detours (even in trial route estimates), increasing wire length and delay.

Bad Pin Placement

Placement Density: Placing cells too densely, even if not causing severe congestion, results in longer average wire lengths compared to a sparser placement.

oIncreased Resistance: Interconnect wires become thinner and taller (to try and mitigate R increase, but R still dominates over C). Via resistance also increases dramatically. This makes the power grid inherently more resistive, leading to higher IR drop (V=I×R).

• Lower Supply Voltage (Vdd): Operating voltages are significantly lower (e.g., < 0.8V). This means the allowable noise margin for IR drop (both static and dynamic) is much smaller (e.g., 5-10% of Vdd is a smaller absolute voltage). Designs become extremely sensitive to voltage variations.
• Higher Current Density: While voltage decreases, the density of transistors increases significantly, leading to higher overall current density (J) in the power grid, especially localized hotspots. Risk of EM.
• Dynamic IR Drop (Voltage Droop): Faster switching speeds and higher localized current demands exacerbate dynamic voltage droop. Providing sufficient instantaneous current through the high-resistance grid requires a very dense decap cell strategy and a robust PDN.
• Complexity of PDN Design: Achieving the required low resistance and meeting IR/EM targets often necessitates using more metal layers for the power grid, wider straps, and significantly more vias, consuming valuable routing resources needed for signals. Balancing power needs with signal routability becomes harder.

7nm Challenges (includes power/interconnect): https://www.wipro.com/blogs/mohit-bansal/the-benefits-and-challenges-of-7nm-technology/