Use area aware synthesis and placement.

Place macros carefully to give maximum std cell placeable area. Use congestion driven placement to reduce high utilization impact on congestion.

oEnsure that partial blockages are not too restrictive. If a region is 50% blocked, and nearby area is full, cells may crowd into corners.

• Create blockage in distributed area. https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009mFGeEAM&pageName=ArticleContent
• If found that one particular module or instances that can be identified in patterns, is crowded at corner, give cell padding.

oRouting Congestion: Macros create “pinch points” or areas of high congestion around the corners and between adjacent macros, making it difficult for the router to connect signals. And creates Routing Detours resulting in longer wire lengths, increased delay, and potentially new timing violations.

• Sub-optimal Standard Cell Placement: tool not able to optimize placement.
• Power Distribution Issues: If a macro is particularly power-hungry, placing it in the middle of the core can cause a significant local IR drop unless the power grid is specifically reinforced in that area.
• Clock Tree Synthesis (CTS) Challenges: Macros can obstruct clock tree routing, making it harder for CTS tools to build a balanced tree with low skew.

oBuffers/inverters for optimization

• Physical only cells added like decap, endcaps, well taps etc.
• CTS structure adds buff/inv.
• Blockages/halos added in floorplan.
• Scan chain reordering, normal FF to scan FF increases area. Hold fix in Scan modes

Based on, on which layer macros has pins, we can drop via on top of that layer or do direct connection on pin layer. Different macros may have different internal structure and hence pins at different layers.

• Power Grid Integrity: Due to lower Vdd and higher current density, the power grid must be extremely robust. This means more metal layers allocated for power
• Pin Placement Complexity: Higher pin counts and tighter bump pitches make I/O pin placement challenging.
• Increased Pin Density & Access: Macros at 7nm often have extremely high pin densities. This requires wider channels, careful orientation and blockages.
• Complex DRCs:
• Timing Impact: Due to high wire resistance