·Inputs for Crosstalk/Noise Analysis:

Timing Libraries (.lib**,** .db**):**

Parasitics (SPEF): Requires detailed parasitic extraction data, including accurate coupling capacitance (Cc​) values between nets, along with resistance (R) and ground capacitance (Cg​). This is crucial as Cc​ is the mechanism for crosstalk.

Netlist:

Constraints (SDC): Standard timing constraints (clocks, exceptions, etc.) are needed to determine timing windows. STA tools use timing windows to determine if aggressor and victim nets can switch simultaneously, making crosstalk delay/noise relevant.

oIn terms ofSTA:

• When in timing path, there is output of combo logic is used as input in same timing path, it forms, loop causing instability and difficulty in modelling timing for that path.
• https://www.intel.com/content/www/us/en/docs/programmable/683323/18-1/avoid-combinational-loops.html
• In terms of DRC: when layer has DPT enabled and layout is forming a loop in such a way that it is not possible to assign mask1/2 to shapes without causing spacing violations.
• https://semiengineering.com/cut-cut-double-patterning-question/
• https://semiwiki.com/eda/1962-fixing-double-patterning-errors-at-20nm/#:~:text=Move%20single%20edges%20as%20opposed,which%20make%20the%20design%20uncolorable.

o Antenna Effect (Plasma-Induced Gate Oxide Damage): During semiconductor manufacturing, plasma etching processes are used to remove material. In these processes, charged particles (ions, electrons) bombard the wafer surface. If a long metal wire (acting like an “antenna”) connected only to a transistor gate is exposed during etching, it can accumulate significant charge from the plasma. If this charge builds up enough voltage, it can exceed the breakdown voltage of the thin gate oxide layer beneath the transistor gate, causing damage (latent defects or immediate breakdown). This damage can lead to reliability issues or functional failure. The risk increases with the Increase in metal area compared to gate area. Which is called antenna ration.

o DRC (Design Rule Check): checks if the physical layout is as per foundry rules, ensure it can be manufactured reliably with acceptable yield.

Types of Rules: Include minimum width, minimum spacing (intra-layer and inter-layer), minimum area, via enclosure, overlap requirements, antenna rules (often checked separately but fundamentally DRCs), density rules, and many complex conditional rules (e.g., end-of-line spacing, notch spacing).

Fixing DRCs:

Spacing Violations: Increase the space between the violating shapes (e.g., move wires further apart).

o Electromigration (EM): The gradual displacement and migration of metal atoms in an interconnect (wire or via) caused by the momentum transfer from flowing electrons. Over time, at high current densities and temperatures, this movement can lead to:

Voids: Depletion of metal atoms in a region, increasing resistance and potentially causing an open circuit (wire break).

Hillocks: Accumulation of metal atoms in another region, potentially causing shorts to adjacent wires.

oFunctional ECO: An Engineering Change Order implemented to fix a logical bug in the design’s functionality or to add/modify a feature. The change originates from an RTL modification.

• RTL code is modified to fix the bug or add the feature.
• The changed RTL is synthesized (often just the affected module).
• Synopsys Formality ECO, Cadence Conformal ECO compares the original synthesized netlist (the one in PnR) with the newly synthesized netlist from the changed RTL.
• The ECO tool identifies the logical differences and generates a set of gate-level changes (ECO patch – add/delete/modify gates and connections) needed to transform the PnR netlist to match the new functionality. This patch is often a sequence of tool commands (add_cell, remove_cell, connect_net, disconnect_net, etc.).

Implementation in PnR: The ECO patch (script) is applied to the PnR database, followed by incremental placement (legalization) and routing of the modified logic.