o Increased Wire Length (Detouring): Due to congestion or blockages, detailed router can detour nets. eGR doesn’t detour to report max congestion. This results in difference in earlied net length estimation causing more RC delay and cell delay if more bufs added.

Accurate Parasitic Extraction (RC Extraction): eGR may use tQrc which is fast but less accurate. Detail routing mostly uses iQrc or QRC for extraction which is more accurate resulting in timing degradation.

o NDRs Used: The most common NDR applied was Double Width, Double Spacing (2W2S) for the main trunk and branch lines of the clock tree. For very critical top-level clock spines, sometimes Triple Width (3W) or wider rules were considered, depending on EM requirements and foundry recommendations.

Using 2W2S Till Leaf Cells:

Generally NO. not necessary and highly undesirable.

Congestion: number of leaf-level clock nets is enormous. Applying 2W2S universally would consume excessive routing resources, especially on lower layers where usually pin connections occur

oTempus/ PT used for STA.

• PT –
• Size_cell
• Fix_eco_drc
• Fix_eco_timing
• Tempus – eco_opt_desing -dev -setup -hold

oupdate_io_latency not done at block level. This ensures proper clock tree built for IO paths and gives feedback to top level tree so tree is balanced for io paths.

• IO constraints like input_delay and output_delay is assumption. Actual delay might be different and hence misscorelation.
• Different derate factors at top level or OCV variation?
• May introduce additional SI effect during top level

oSAIF contains Activity over time window but it doesn’t have timestamp for each change in signal. VCD notes each timestamp for change.

• So Saif has overall toggle count over time but not exact waveform of change.
• Saif is relatively less in size wherein VCD contains more detailed info and hence large in size.

If “MyIP” is instantiated at top level netlist, but if no definition is found of MyIP, then it becomes unresolved reference.

my_module u1 (.clk(clk), .rst(rst)); // ‘my_module’ is not defined anywhere in netlist or not found definition through .lib as well.

Blackbox:

module my_module (input clk, input rst);

// No internal implementation here

Endmodule

In this case, my_module is blackbox, as it is defined but only ports, no internal logic defined.