o Target Utilization at Start: The initial target core utilization for PnR typically ranges from 50% to 70%.

Lower utilization (e.g., 50-60%) provides more whitespace, making routing easier, reducing congestion, potentially improving timing (less detour), and offering more flexibility for CTS and ECOs. This is often preferred for high-performance designs or designs with known congestion challenges.

Higher utilization (e.g., 65-70%, sometimes even higher for specific blocks) aims to minimize die area (cost). However, it increases the risk of congestion, may make timing closure harder, and leaves less room for post-route optimizations and ECOs.

oSwitching State: The switching state consumes significantly more power in CMOS circuits. This is called dynamic power and has two main components:

Switching Power: Charging and discharging load capacitances (Psw​=αCVdd2​f, where α is activity factor, C is load capacitance, Vdd is supply voltage, f is frequency).

Short-Circuit Power: For a brief moment during switching, both PMOS and NMOS transistors can be partially ON, creating a direct path from VDD to VSS.

oVoltage islands (or power domains operating at different voltage levels) are created primarily to reduce overall power consumption (both dynamic and static).

Dynamic Power Reduction: Pdynamic​∝Vdd2​. By operating non-performance-critical blocks (islands) at a lower supply voltage (e.g., 0.7V) compared to performance-critical blocks (e.g., 0.9V), the dynamic power consumption of the low-voltage blocks is significantly reduced.

Static Power Reduction: Pstatic​∝Vdd​×Ileakage​. Lowering Vdd directly reduces static power. Additionally, leakage current (Ileakage​) itself often decreases at lower voltages.

Sources of Variation: The primary sources of variation that necessitate derates are:

·PVT (Process, Voltage, Temperature) Variations: These are inter-chip variations.

o Process: Variations in manufacturing (e.g., lithography wavelength, defects) can alter transistor parameters like oxide thickness, dopant levels, and physical dimensions (W/L), which in turn affect threshold voltage (Vt​) and current (I), and thus cell delay. Dies at the center of a wafer are more accurate than those at the periphery.