oMin Pulse Width (MPW) Violation: A timing check ensuring that the duration of a clock pulse (either the high phase or the low phase) at the clock pin of a sequential element (or other sensitive pins like asynchronous resets) is sufficiently long for the cell to function correctly. Libraries specify min_pulse_width_high and min_pulse_width_low requirements. A violation occurs if the actual pulse width reaching the pin is shorter than the required minimum.
Causes:
Duty Cycle Distortion: Unequal rise/fall delays in the clock tree buffers/inverters can shrink either the high or low phase of the clock pulse as it propagates.
Glitches: Noise or races in combinational logic generating clocks or asynchronous resets can create very short pulses (glitches).
Clock Gating Issues: Improperly timed enable signals on clock gates can sometimes clip the clock pulse.
How to Solve It:
- Balanced Clock Tree Cells: Use clock buffers/inverters with symmetrical rise/fall delays to minimize duty cycle distortion during CTS. Using inverters is preferred.
- If it is due to glitch/ noise, then address crosstalk.
- Fix Clock Gating Timing: Ensure the clock gating enable signal meets its setup/hold requirements relative to the clock input of the ICG cell.
- Increase Clock Period/Adjust Duty Cycle: If the MPW violation is fundamental to the clock generation or distribution at the target frequency/duty cycle, adjusting the clock source itself might be needed (architectural change).