Configure the tool to find the required library files (.lib, .lef).
- Innovus:
- ICC2: set_app_var search_path ./libs ; set_app_var target_library {slow.db} ; set_app_var link_library “* slow.db” (Specify LEF via read_tech_lef, read_cell_lef or read_ndm)
- Load Physical Libraries (.lef**):** Read the technology LEF and the standard cell/macro LEF files.
Innovus: Handled by init_design if paths are set, or read_lef tech.lef cells.lef
ICC2: read_tech_lef tech.lef ; read_cell_lef cells.lef (or read_ndm for NDM libraries which bundle lib/lef)
- Read the Netlist: Load the synthesized gate-level Verilog netlist.
Innovus: read_netlist design.v
ICC2: read_verilog design.v
- Initialize the Design / Create Floorplan: Create the initial design structure and floorplan boundary. This often requires specifying the top-level module.
Innovus: init_design (This command often combines reading LEF, netlist, and creating an initial floorplan). It might require set init_design_netlist and set init_design_top_cell first.
ICC2: link_design (links the logical netlist to library definitions); initialize_floorplan (creates the initial floorplan boundary).
Apply Timing Constraints: Read the SDC file to apply timing constraints.
Innovus: read_sdc design.sdc
ICC2: read_sdc design.sdc
(Optional) Apply Power Intent: If using UPF/CPF, load these files.
Innovus: read_upf design.upf
ICC2: load_upf design.upf ; commit_upf
Perform Sanity Checks: Run initial check* commands (e.g., checkDesign, check_timing) to verify the loaded data.