Posts on Physical Design Interview Guide

Different CTS types? What are benefits of those?

Sat, 23 Aug 2025 00:00:00 +0000

1. Conventional / Single Point CTS

This is the standard approach used for lower-frequency designs with fewer “sinks” (flip-flops/registers).

Structure: It has a single clock source that distributes the signal to every corner of the design. The “point of divergence” (where the paths split) is right at the clock source.
Benefits:
- High Power Efficiency: Because clock gating is typically done near the source, large sections of the tree can be shut off, saving significant dynamic power.
- Simplicity: It is the easiest to implement using standard EDA tool flows.
Trade-offs: * OCV Sensitivity: Because the clock paths are largely “uncommon” (they don’t share much of the same wire/buffer path), manufacturing variations (OCV) affect each branch differently, leading to higher skew.
- High Insertion Delay: The signal has to travel through many levels of buffers to reach the entire chip.

2. Clock Mesh Structure

This is the most robust structure, creating a dense grid of shorted wires driven by “mesh drivers.”

How to build/synthesize the clock tree? What types of cells are used?

Sat, 23 Aug 2025 00:00:00 +0000

o Conventional CTS (Buffer/Inverter Tree): The most common approach. The tool starts from the sinks and works backward or starts from the root and works forward, clustering nearby sinks, inserting buffers/inverters to meet skew, latency, and DRC targets, and progressively building a tree structure. The exact topology isn’t strictly predefined but emerges based on sink locations and optimization goals. Modern tools use sophisticated algorithms (e.g., clock concurrent optimization - CCOpt) that optimize the clock tree and logic paths concurrently.

Pros and cons of H-tree? Advantage of using both buffers and inverters?

Sat, 23 Aug 2025 00:00:00 +0000

o H-Tree:

Advantages:

Zero Skew (Ideal): Theoretically capable of achieving zero skew if sinks are perfectly distributed and the tree is perfectly balanced.

Symmetric Structure: Predictable and regular routing pattern.

Disadvantages:

Impractical for Real Designs: Assumes uniform sink distribution, which rarely occurs. Blockages and routing obstacles disrupt the ideal structure.

High Insertion Delay: Can lead to long paths from the root to sinks.

Resource Intensive: Can consume significant routing area, especially on preferred layers.

What are inputs required to star CTS?

Sat, 23 Aug 2025 00:00:00 +0000

Placement Database: The design database after placement is complete, containing the locations of all standard cells (including clock sinks like flip-flops and clock gates) and macros. – it covers Timing lib. Tech lef, std cell lef, SDC etc.

CTS Specification File .ctstch**,** .cts_spec**,** This file (or equivalent tool settings) provides detailed instructions for building the clock tree:

Target Skew: Maximum acceptable skew between sinks in the same clock domain or skew group.
Target Max/Min Latency: Desired range for insertion delay.
Target Max Transition: Maximum allowed transition time for clock nets.
Buffer/Inverter List: Specifies the list of buffers and inverters the tool is allowed to use for building the tree (often restricts to specific drive strengths or balanced cells).
DRC Constraints: Max capacitance, max fanout limits specifically for clock nets.
NDR (Non-Default Rules): Specifies special routing rules (e.g., double width, double spacing, shielding) to be used for clock nets to improve signal integrity and reliability.
Routing Layers: Preferred top and bottom metal layers for clock routing.
Clock Tree Exceptions: Defines pins to be treated specially:
- Stop/Sink Pins (Default): Normal clock endpoints to be balanced.
- Exclude Pins: Excluded from skew/latency balancing but still receive the clock and DRV fixing (e.g., output ports, Multiplexer select pin )
- Ignore Pins: Completely ignored by CTS balancing and DRC fixing (e.g., non-clock pins driven by clocks, test pins).
- Float Pins: Similar to Exclude pins but allow specifying a pin delay range for balancing (used for macro models).
- Non-stop pins: trace through the endpoints that are normally considered as endpoints of the clock tree. Ex, The clock pin of sequential cells driving generated clock are implicit non-stop pins. Clock pin of ICG.
Skew Groups: Defines groups of sinks that should be balanced together, potentially with different skew targets than other groups.
Clock Tree Structure Hints: May allow specifying preferred structures (e.g., H-tree for certain branches) or buffer placement constraints. Multi tap etc.

CTS Spec File Contents: https://ivlsi.com/cts-spec-file-vlsi-physical-design/

What are the checks after CTS?

Sat, 23 Aug 2025 00:00:00 +0000

1. Clock Tree Reports:

Skew Report: Verify that the achieved maximum skew (global and potentially per skew group) meets the target specified in the CTS spec/constraints.

Latency Report: Check the minimum and maximum insertion delays. Ensure they are within acceptable ranges or meet specific targets.

DRC Report (CTS Specific): Check for violations of max_transition, max_capacitance, max_fanout specifically on the clock tree buffers/inverters and nets.

Duty Cycle and MPW violatons.

Clock tree power.

What is clock latency? How to reduce latency?

Sat, 23 Aug 2025 00:00:00 +0000

o Clock Latency (Insertion Delay): The time it takes for the clock signal to propagate from its source (the point where the clock is defined, e.g., a primary input port) to the clock pin of a specific sequential element (sink pin, e.g., a flip-flop’s CK pin).

Source Latency: Delay from the actual clock origin (e.g., crystal oscillator) to the clock definition point in the design (defined using set_clock_latency -source). This models external delay.

What is clock skew? What causes skew? How to balance skew?

Sat, 23 Aug 2025 00:00:00 +0000

o Clock Skew: The difference in arrival time of the clock at capture FF and launch FF.

Local Skew: Skew between two specific, related flops (e.g., launch and capture flop of a timing path).

Global Skew: The difference between the maximum and minimum clock latency across all sinks in a domain.

Causes of Skew:

Different Path Lengths: The physical distance (wire length) from the clock root to different sinks varies due to their placement locations.

Where should clock gaters be placed (near sink or source)?

Sat, 23 Aug 2025 00:00:00 +0000

oIf you place ICG near to source, dynamic power consumption will reduce. This is because most of the clock buffers are in fanout of clock gater. These clock buffers will not toggle when clock gating is enabled.

But placing ICG near to source increases the uncommon paths. These uncommon paths can behave differently, so during STA these need to be taken into account that extra uncertainty.
If you place ICG near to sink, most of the clock buffers are in common path. It is easy to met timing compared to scenario-1.
But at the same time dynamic power consumption is increased.
Remember, there is trade-off between power and timing.
Ideally, Integrated Clock Gating (ICG) cells should be placed physically close to the group of flip-flops (sinks) they are gating.

Improve CTS Balancing: CTS tools balance delay up to the inputs of the ICG cells. Placing the ICG close to the sinks means the final, unbuffered gated clock segment is short and contributes less variable delay, making overall skew balancing more predictable.

How are TEST mode & FUNC mode defined and constrained?

Fri, 22 Aug 2025 00:00:00 +0000

oDefining Modes: Different operating modes are : Functional mode - FUNC and test Modes: Scan Shift, Scan Capture, BIST

Defined in MCMM setup with create_constraint_mode command and given separate SDC of each mode.
Separate SDC Files: Each SDC file contains the appropriate set_case_analysis settings, relevant clock definitions (test clocks might differ from functional clocks), and potentially different timing exceptions or I/O delays specific to that mode.
Mode-Specific Constraints within one SDC: Less commonly, complex logic within a single SDC file might be used to apply constraints conditionally, but separate SDCs or set_case_analysis are standard.

Checking Simultaneously (MMMC):

How do you fix setup violations? What if upsizing/layer change isn't possible?

Fri, 22 Aug 2025 00:00:00 +0000

o We need to reduce cell delay or Net delay or use more skew – can use various methods for each.

o Reduce Cell Delay:
oCell Sizing (Upsizing): Increase drive strength of cells on the critical path. (Effective for small to moderate violations).
oVT Swapping (Lowering Vt): Swap cells to faster, lower-Vt variants (HVT->SVT->LVT). (Effective, but increases leakage).
oReduce amount of buffering if excessive bufs are added.
o Reduce Net Delay:

How to analyze a timing report?

Fri, 22 Aug 2025 00:00:00 +0000

oPath Summary:

Startpoint: Where the path begins (input port or flop clock pin).

Endpoint: Where the path ends (output port or flop data input pin).

Path Group:

Path Type: Setup, Hold, Recovery, Removal, Min Pulse Width, etc.

Slack:

Data Arrival Time Path: Details the delay contribution of each element along the data path:

Clock Network Delay (Launch): Latency from clock source to launch flop clock pin (relevant post-CTS).

Clock-to-Q Delay: Delay through the launch flop.

If setup & hold are clean but there are clock DRVs, can the block be closed? How to identify and fix clock DRVs?

Fri, 22 Aug 2025 00:00:00 +0000

oNO. Even if setup and hold timing checks pass, significant Design Rule Violations (DRVs) either on data or clock needs to be fixed.

Reliability: Slow transitions (max_transition violation) make sequential elements susceptible to noise, glitches, and potential metastability

Timing Accuracy: buffers/inverters are characterized based on expected input transitions and output loads. Violating max_transition or max_capacitance means the library timing models used for setup/hold analysis are inaccurate, invalidating the “clean” timing result. The actual delays might be worse.

If there's no setup margin, how to fix hold?

Fri, 22 Aug 2025 00:00:00 +0000

oIf setup and hold both are critical on same path, check if it is exact same path or if there is any diversion from combo logic in setup and hold timing path.

If there is any diversion, add delay at that point so hold can be fixed without touching setup critical path.

If timing path is exactly same and having setup and hold violations, there could be two reasons,
Crosstalk impact – crosstalk will add delay in setup and reduce it in hold. Impacting adversely both setup and hold. Fixing crosstalk should give margin to fix setup and hold.
If there is no crosstalk, there can be very high setup and hold time requirement from endpoint. (may happen with reg2mem paths)
Check if such cells can be replaced with less access time cell.
To get margin in setup and hold both, you need to use cell with less delay variation across SS-FF corners.
Use LVT cells in data path instead of SVT/HVT. Use low drive strength cells and reduce net legth so that OCV impact can be reduced giving margin for setup and hold.

What are the different types of timing path groups?

Fri, 22 Aug 2025 00:00:00 +0000

o Register-to-Register (Reg2Reg): Starts at the clock pin of a launch flip-flop/latch and ends at the data input pin (e.g., D) of a capture flip-flop/latch. Both launch and capture elements are controlled by related clocks (often the same clock). This is the most common type of path analyzed for setup/hold within a synchronous design.

Input-to-Register (In2Reg): Starts at a primary input port of the design and ends at the data input pin of a sequential element. Constrained by set_input_delay.

What is a via pillar? What is need of it?

Fri, 22 Aug 2025 00:00:00 +0000

o Via Pillar: A structure used in advanced process nodes (like FinFET nodes) to create a lower-resistance vertical connection between metal layers compared to traditional single vias or via arrays. It typically consists of:

Stacked, short metal segments (“fingers”) on intermediate metal layers, aligned vertically.

These segments are connected by vias above and below, essentially forming a “pillar” of alternating via and short metal bar segments running vertically through multiple layers.

What is CPPR (Common Path Pessimism Removal)? How is crosstalk considered in it for setup and hold?

Fri, 22 Aug 2025 00:00:00 +0000

oOCV analysis (like AOCV/POCV or simple derating) applies different delay values for ’early’ (fast) and ’late’ (slow) conditions.

For a setup check, the launch clock path uses late delays, and the capture clock path uses early delays. For a hold check, it’s reversed.

However, both clock paths often share a common segment starting from the clock root before diverging. Applying both early and late derates simultaneously to this same physical common path introduces artificial pessimism because the common path cannot physically be both fast and slow at the exact same instant.

What is min pulse width violation? How to solve it?

Fri, 22 Aug 2025 00:00:00 +0000

oMin Pulse Width (MPW) Violation: A timing check ensuring that the duration of a clock pulse (either the high phase or the low phase) at the clock pin of a sequential element (or other sensitive pins like asynchronous resets) is sufficiently long for the cell to function correctly. Libraries specify min_pulse_width_high and min_pulse_width_low requirements. A violation occurs if the actual pulse width reaching the pin is shorter than the required minimum.

What is the difference between MCP (Multicycle Path) and false path?

Fri, 22 Aug 2025 00:00:00 +0000

oFalse Path (set_false_path):

Specific path between a startpoint and endpoint cannot be logically sensitized during normal circuit operation. Although a physical path exists, signals will never actually propagate from the startpoint to the endpoint along that path under functional conditions

STA Action: The tool completely ignores this path for all timing analysis (setup, hold, DRCs). It assumes the path has infinite time to propagate.

When to Use: Only for paths that are guaranteed to be functionally impossible or irrelevant to the timing modes being analyzed.

Explain SI. What does crosstalk noise/glitch mean?

Thu, 21 Aug 2025 00:00:00 +0000

o Signal Integrity (SI): Quality of an electrical signal as it travels from a driver to a receiver through an interconnect. Major SI concerns include:

o Crosstalk: Unwanted coupling between adjacent signal nets.

o IR Drop: Voltage drop on the power/ground network affecting cell performance.

o Electromigration (EM): Reliability issue due to metal migration under high current density.

o Timing Jitter/Phase Noise: Variations in the timing of signal edges, especially critical for clocks.

How do you decide which scenarios/corners to use for PnR vs. Signoff?

Thu, 21 Aug 2025 00:00:00 +0000

The selection involves a trade-off between PnR runtime/effort and signoff accuracy/coverage.

Signoff: Aims for comprehensive coverage of all conditions the chip might experience. It typically includes:

Multiple PVT Corners: Extremes of Process (SS, FF, SF, FS), Voltage (min, max), and Temperature (min, max), plus typical (TT).

Multiple RC Corners: Worst/Best RC combinations (RCworst, RCbest, Cworst, Cbest, potentially crosstalk corners).

Multiple Modes: Functional modes, test modes (Scan Shift, Scan Capture, BIST), potentially low-power modes.

How do you fix crosstalk violations? Why Downsize the Aggressor Driver?

Thu, 21 Aug 2025 00:00:00 +0000

1. Increase Spacing: Physically increase the distance between the victim and aggressor nets during routing. This directly reduces coupling capacitance (Cc). (Most effective but consumes routing area).

Shielding: Insert a static net (tied to VDD or VSS) between the victim and aggressor. The shield net intercepts coupling capacitance, preventing interference. This can add coupling cap on signal net causing delay.

Layer Change: Route the victim or aggressor on different metal layers for a portion of their length to reduce parallel run length and coupling.

How do you handle cases of IR drop—both static and dynamic—especially if the standard methods are not applicable?

Thu, 21 Aug 2025 00:00:00 +0000

o Handling Static IR Drop: Static IR drop is primarily due to the resistance of the power grid (Vdrop=Iavg×Rgrid). If you cannot improve Rgrid (by widening straps/adding vias):

Reduce Average Current (Iavg):

Downsize Non-Critical Cells: Replace cells contributing significantly to static leakage in the affected region with smaller drive-strength variants (if timing permits).

VT Swapping (High VT): Swap cells to higher Vt variants (LVT -> SVT -> HVT) in the affected area. Higher Vt cells have significantly lower leakage current. This requires available timing slack.

How do you instruct your tools to resolve post-clock violations? What role does “useful skew” play in these scenarios?

Thu, 21 Aug 2025 00:00:00 +0000

oEnable Post-CTS/Post-Route Optimization:

Innovus: optDesign -postCTS (after CTS), optDesign -postRoute (after routing). These commands invoke timing-driven optimization engines.
ICC2: clock_opt -stage cts_optimize (after CTS build), route_opt (performs routing and optimization iteratively).
Specify Effort Levels: Increase the optimization effort.
Innovus: setOptMode -effort high|extreme
ICC2: Options within place_opt, clock_opt, route_opt to control effort (e.g., -effort high).
SI-Aware Optimization: Ensure Signal Integrity (crosstalk) aware optimization is enabled if SI violations are contributing to timing issues.
Innovus: setOptMode -crosstalkAware true
ICC2: set_si_options -delta_delay true -glitch true; route_opt -xtalk_driven
Role of “Useful Skew”:

Setup Violation Fixing:

How do you interpret LVS report mismatches?

Thu, 21 Aug 2025 00:00:00 +0000

oIncorrect Nets / Connectivity Errors: This section details discrepancies in how nets are connected.

Shorts: When Schematic has more nets but layout has less nets, layout has short.

Opens: A single net in the schematic corresponds to two or more unconnected nets in the layout.

Incorrect Instances / Devices: Discrepancies in the number or type of devices.

Missing Devices: A device present in the schematic is not found in the corresponding location/netlist in the layout.

How do you solve/fix IR drop issues (at placement, ECO stage)?

Thu, 21 Aug 2025 00:00:00 +0000

o Fixing IR drop involves 1) strengthening the Power Distribution Network (PDN) to reduce its resistance or 2) reducing the current drawn by the logic.

During Placement/Floorplan (Preventative)
Robust PDN Design: Plan a dense power grid using wide straps/rings on low-resistance metal layers with ample vias
Macro Placement: Place high-power macros near power sources or ensure they have strong connections to the power grid.
Cell Placement: Avoid clustering high-power or high-switching activity cells in one area. Use density controls.
During Post-Route Optimization / ECO Stage:
Strengthen PDN:
Add/Widen Power Straps: Introduce more power/ground stripes in areas with high voltage drop or increase the width of existing straps.
Add Power Vias: Increase the number of vias connecting different layers of the power grid, at connections to cell rails, to reduce vertical resistance.
Add Decap Cells (Primarily for Dynamic IR):
Reduce Current Draw:
Cell Downsizing: Replace high-power cells in the violating region with smaller drive-strength equivalents, if no timing violations.
VT Swapping (Higher Vt): Swap cells to higher-Vt to reduce leakage current (helps static IR) and slightly reduce peak dynamic current (helps dynamic IR), If no timing issues.
Spread High-Activity Cells: If dynamic IR drop is caused by simultaneously switching cells clustered together, try spreading these cells apart during ECO placement

How to perform manual clock tuning during ECOs?

Thu, 21 Aug 2025 00:00:00 +0000

oIt requires careful analysis and is typically done for critical paths where there is no scope in data path.

For setup:
Early the launch clock or delay the capture clock so skew can be increased which helps in setup violation. With this you are reducing the skew in path before and after this path. So there should be setup margin in both adjacent paths and hold margin in same path.
For Hold:
Delay the launch clock or early the capture clock so skew can be reduced which helps in hold violations. Path should have setup margin. And path before and after this path should have hold margin as for them it will increase the skew.
Analyze Clock Path:
Trace the launch and capture clock paths for the violating timing path.
Identify existing buffers/inverters on these clock paths, their drive strengths, and locations.
Understand the common clock path and the diverging points.
Make desired changes after diverging point, ex, upsize, downsize, add delay based on setup or hold fix.
Apply ECO in PNR tool and run STA to verify fixes

In a low power project with multiple corners (e.g., low_svs, turbo), how do you choose the appropriate timing corner for each step?

Thu, 21 Aug 2025 00:00:00 +0000

oIn a low-power project with specific operating performance points (OPPs) like:

“low_svs” (Low Standard Voltage Swing, likely a power-saving mode)
“turbo” (a high-performance mode, likely at a higher voltage),

Setup Analysis:

low_svs Mode: Analyze setup at the slowest process corner (SS/SSG) combined with VddL and worst-case temperature (often high temp for CMOS). This is SSG_VddL_HighTemp_RCworst. This represents the slowest the logic will be in low power mode.

turbo Mode: Analyze setup at the slowest process corner (SS/SSG) combined with VddH and worst-case temperature. This is SSG_VddH_HighTemp_RCworst. This is the absolute performance bottleneck.

IR flow based on vector or vectorless? Is toggle rate given? twf fiile, what's its contents?

Thu, 21 Aug 2025 00:00:00 +0000

o Vector-based Analysis: Used VCD (Value Change Dump) or FSDB files generated from gate-level simulations of specific, high-activity scenarios (e.g., boot-up sequence, high-performance benchmark execution, specific test modes). These vectors provide accurate, cycle-by-cycle switching activity for those specific scenarios, allowing us to identify peak IR drop and EM stress under known critical operating conditions

Vectorless Analysis: To ensure broader coverage and identify potential worst-case scenarios not easily captured by specific VCDs, used vectorless dynamic analysis.
Usually Vectorless is often used earlier in the flow for faster feedback, while vector-based analysis with critical scenarios mandatory for final signoff
Given Toggle Rate? à Yes, toggle rates were used, primarily for:
Static IR Drop/Power Analysis: Average toggle rates (often derived from synthesis estimates, statistical propagation, or averaged from simulations) used along with leakage data to calculate the average current for static analysis.
Vectorless Dynamic Analysis (Seeding): Some vectorless techniques might use initial toggle rate information as a starting point for activity propagation or statistical analysis.
Given TWF file? Yes, TWF (Timing Window File) files were used as input for dynamic analysis, especially for vectorless methods
A TWF file contains information about the possible switching time windows for signals in the design.
For each net or pin, it specifies the earliest and latest possible time (relative to the clock edge) that a signal transition (rise or fall) can occur

What are Physical Verification checks?

Thu, 21 Aug 2025 00:00:00 +0000

oDRC (Design Rule Check): Verifies that the layout geometry adheres to the manufacturing constraints (design rules) specified by the foundry for the target technology node. This includes checks for minimum width, spacing, area, enclosure, overlap, etc., for all layers (metal, poly, diffusion, vias, etc.). Ensures the layout can be physically manufactured with acceptable yield.

LVS (Layout Versus Schematic): Compares GDS(Layout) vs schematic(Netlist). It verifies that the layout correctly implements the intended logic in netlist. It checks, device types, and device parameters (like transistor W/L). Checks for shorts, opens, incorrect connections, missing/extra devices, and parameter mismatches.

What is Antenna Effect? How to solve antenna violations?

Thu, 21 Aug 2025 00:00:00 +0000

o Antenna Effect (Plasma-Induced Gate Oxide Damage): During semiconductor manufacturing, plasma etching processes are used to remove material. In these processes, charged particles (ions, electrons) bombard the wafer surface. If a long metal wire (acting like an “antenna”) connected only to a transistor gate is exposed during etching, it can accumulate significant charge from the plasma. If this charge builds up enough voltage, it can exceed the breakdown voltage of the thin gate oxide layer beneath the transistor gate, causing damage (latent defects or immediate breakdown). This damage can lead to reliability issues or functional failure. The risk increases with the Increase in metal area compared to gate area. Which is called antenna ration.

What is DRC (Design Rule Check)? How to fix drcs if in huge numbers?

Thu, 21 Aug 2025 00:00:00 +0000

o DRC (Design Rule Check): checks if the physical layout is as per foundry rules, ensure it can be manufactured reliably with acceptable yield.

Types of Rules: Include minimum width, minimum spacing (intra-layer and inter-layer), minimum area, via enclosure, overlap requirements, antenna rules (often checked separately but fundamentally DRCs), density rules, and many complex conditional rules (e.g., end-of-line spacing, notch spacing).

Fixing DRCs:

Spacing Violations: Increase the space between the violating shapes (e.g., move wires further apart).

What is EM (Electro migration)? How to solve EM violations?

Thu, 21 Aug 2025 00:00:00 +0000

o Electromigration (EM): The gradual displacement and migration of metal atoms in an interconnect (wire or via) caused by the momentum transfer from flowing electrons. Over time, at high current densities and temperatures, this movement can lead to:

Voids: Depletion of metal atoms in a region, increasing resistance and potentially causing an open circuit (wire break).

Hillocks: Accumulation of metal atoms in another region, potentially causing shorts to adjacent wires.

What is functional vs timing ECOs? How to implement them?

Thu, 21 Aug 2025 00:00:00 +0000

oFunctional ECO: An Engineering Change Order implemented to fix a logical bug in the design’s functionality or to add/modify a feature. The change originates from an RTL modification.

RTL code is modified to fix the bug or add the feature.
The changed RTL is synthesized (often just the affected module).
Synopsys Formality ECO, Cadence Conformal ECO compares the original synthesized netlist (the one in PnR) with the newly synthesized netlist from the changed RTL.
The ECO tool identifies the logical differences and generates a set of gate-level changes (ECO patch – add/delete/modify gates and connections) needed to transform the PnR netlist to match the new functionality. This patch is often a sequence of tool commands (add_cell, remove_cell, connect_net, disconnect_net, etc.).

Implementation in PnR: The ECO patch (script) is applied to the PnR database, followed by incremental placement (legalization) and routing of the modified logic.

What is IR drop (Static/Dynamic)? Why consider it?

Thu, 21 Aug 2025 00:00:00 +0000

·For power analysis, each cell’s power dissipation has been characterized in the library (.lib) file. For leakage power, the EDA tool simply adds up the leakage power of each cell. (Note: Leakage power is usually state dependent) For dynamic power, the EDA tool either estimates net capacitance before P&R or calculates net capacitance after P&R. The designer has to provide the toggle rate. This can be based on educated guess, experience, simulation, or emulation.

What is LVS and Inputs required? Difference between schematic and layout views? Is it a functional check?

Thu, 21 Aug 2025 00:00:00 +0000

oLVS (Layout Versus Schematic): A critical physical verification process that compares the electrical circuit extracted from the physical layout database (e.g., GDSII, OASIS) against the intended circuit described by the source schematic netlist (e.g., SPICE or Verilog netlist).

Inputs:
Layout Database: The physical layout design file (GDSII, OASIS)
Source Netlist: The “golden” netlist representing the intended circuit schematic (e.g., SPICE netlist for custom designs, Verilog netlist for digital designs).
Rule Deck: Provided by the foundry, this file tells the LVS tool how to identify devices (transistors, resistors, capacitors, diodes) from the layout layers, how to determine connectivity, and how to extract parameters (like W/L for transistors).
Configuration/Setup Files: Files to control the LVS run, specify top cells, map power/ground names, define device properties to compare, set tolerances, etc.
Schematic View vs. Layout View (in LVS context):

Schematic View: Circuit from Golden netlist.

What is the difference between cworst/rcworst and C / RC corners? Why do we need to consider different RC corners?

Thu, 21 Aug 2025 00:00:00 +0000

o Traditional Corners (Simplified View - often just called C corners initially): Used for short nets where resistance can be ignored or very less.

Cworst (Maximum Capacitance, Cmax): Models process variations that maximize interconnect capacitance (e.g., wider wires, thicker metal, smaller spacing, higher dielectric constant). Often assumes minimum resistance for these conditions (though not always explicitly linked). Used primarily for setup timing analysis (longest path delay).

Cbest (Minimum Capacitance, Cmin): Models process variations that minimize interconnect capacitance (e.g., narrower wires, thinner metal, larger spacing, lower dielectric constant). Often assumes maximum resistance. Used primarily for hold timing analysis (shortest path delay).

Why applying a hold ECO causes legalization errors?

Thu, 21 Aug 2025 00:00:00 +0000

oA “cell cannot be legalized” error during an ECO (especially a hold ECO, which often involves adding buffers) means the PnR tool cannot find a valid, DRC-clean placement location for the newly added or modified cells that aligns with the site rows and doesn’t overlap with other cells.

High Cell Density/Congestion: There’s simply no physical space (empty sites) to place the new buffer without causing overlaps.

Filler cells not removed from the design.

Can we see negative setup and hold values in the library? Why? What is the impact?

Wed, 20 Aug 2025 00:00:00 +0000

Yes, it is possible and quite common to see negative setup and hold times specified in standard cell timing libraries (.lib).

There are internal delays along the clock path and data path within the cell, from the input pins to the internal latch.

Negative Setup: If the internal clock path delay is significantly longer than the internal data path delay plus the internal latch’s intrinsic setup time, the data pin (D) can actually change after the active clock edge at the clock pin (CK) and still be captured correctly.

Difference between Static and Dynamic power. How can dynamic power be fixed/reduced?

Wed, 20 Aug 2025 00:00:00 +0000

o Static Power: Power consumed when the circuit is powered ON but not actively switching. It’s primarily due to leakage currents flowing through transistors that are supposed to be OFF.

Main Components: Subthreshold leakage, gate leakage, junction leakage.

Factors: Increases significantly with lower threshold voltages (Vt) and at smaller technology nodes. Also increases with temperature.

Dynamic Power: Power consumed during the switching of logic states (when signals transition between ‘0’ and ‘1’).

Explain CMOS technology basics

Wed, 20 Aug 2025 00:00:00 +0000

oCMOS stands for Complementary Metal-Oxide-Semiconductor. It’s the dominant technology for constructing integrated circuits.

oComplementary: It uses both NMOS (N-channel Metal-Oxide-Semiconductor) and PMOS (P-channel Metal-Oxide-Semiconductor) transistors, typically paired together.

oStructure:

o**NMOS:** Conducts current (electrons) when its gate voltage is high (logic '1'). Built on a P\-type substrate.

o**PMOS:** Conducts current (holes) when its gate voltage is low (logic '0'). Built on an N\-type substrate (or N\-well).

oBasic Inverter: The fundamental CMOS gate is the inverter. It consists of one PMOS transistor connecting the output to VDD (power supply) and one NMOS transistor connecting the output to VSS (ground).

Explain physical-only cells. What is the need for physical cells?

Wed, 20 Aug 2025 00:00:00 +0000

o Decap Cells (Decoupling Capacitors): These are essentially capacitors (often MOSCAPs) placed near switching logic.

Need: to supply instantaneous current demands during fast switching events, stabilizing the power supply voltage (VDD/VSS) and mitigating dynamic IR drop and voltage noise on the power grid

Filler Cells: These cells fill the empty spaces left in standard cell rows after placement and optimization. They typically only contain VDD/VSS connections and substrate/well contacts.

Need: Ensure N-well and substrate continuity for proper biasing. Provide continuous power rail connections along the rows. Required for manufacturability (uniform density for CMP - Chemical Mechanical Polishing).

How do you create a voltage area in floorplan? What is the difference between a voltage domain and a power domain?

Wed, 20 Aug 2025 00:00:00 +0000

o Creating a Voltage Area (Physical Implementation): A voltage area is a physical region on the chip floorplan designated to contain logic operating at a specific voltage level different from other regions, or logic that can be power-gated:

Define the physical boundary (coordinates) of the region- create_voltage_area

Associate this region with a specific power domain defined in the UPF/CPF.

cells belonging to the corresponding power domain are placed within this physical voltage area during placement.

How do you decide if the final netlist is good to go for PnR?

Wed, 20 Aug 2025 00:00:00 +0000

oClean Sanity Checks: The netlist must pass all critical sanity checks:

No fatal errors in check_design / check_netlist (no multi-driven nets, no floating inputs on critical paths, correct connectivity).

No unresolved references (check_library passes, all cells have lib/lef).

No critical errors in check_timing (all clocks defined, critical paths constrained, no unconstrained registers intended to be clocked). Minor unconstrained paths might be acceptable if understood and deemed non-critical or intended false paths.

How do you initialize the design if given netlist, SDC, and lib?

Wed, 20 Aug 2025 00:00:00 +0000

Configure the tool to find the required library files (.lib, .lef).

Innovus:
ICC2: set_app_var search_path ./libs ; set_app_var target_library {slow.db} ; set_app_var link_library “* slow.db” (Specify LEF via read_tech_lef, read_cell_lef or read_ndm)
Load Physical Libraries (.lef**):** Read the technology LEF and the standard cell/macro LEF files.

Innovus: Handled by init_design if paths are set, or read_lef tech.lef cells.lef

ICC2: read_tech_lef tech.lef ; read_cell_lef cells.lef (or read_ndm for NDM libraries which bundle lib/lef)

How do you plan the die size and estimate the chip area?

Wed, 20 Aug 2025 00:00:00 +0000

o Gather Inputs:

Gate Count: Number of standard logic gates from synthesis (excluding memories/macros).

Memory/Macro Area: Total area required for all hard macros, RAMs, ROMs, IP blocks (obtained from their datasheets or abstracts).

IO Count: Number of Input/Output pads/bumps required.

Technology Information: Gate density (gates/mm²) for the target standard cell library, standard cell height, required IO pad dimensions/pitch.

Target Utilization: The desired percentage of the core area that will be occupied by standard cells and macros after placement.

How to place macros?

Wed, 20 Aug 2025 00:00:00 +0000

oAnalyze Connectivity (Flylines) – all fanin, all_fanout.

Use trace macro feature of Innovus.

Group by Hierarchy/Connectivity

Consider Data Flow:

Periphery Placement: Generally place macros around the edges of the core area, leaving the central area for standard cells. This simplifies power delivery to macros and avoids blocking standard cell placement/routing in the core center.

Pin Accessibility: Orient macros so their pins face towards the core logic they connect to, minimizing wire length and routing complexity.

What are the differences between lower technology nodes and higher nodes?

Wed, 20 Aug 2025 00:00:00 +0000

Feature	Lower Nodes (e.g., ≤7nm, 5nm, 3nm)	Higher Nodes (e.g., ≥12nm, 28nm)
Transistor Architecture	FinFETs, transitioning to Gate-All-Around (GAA) FETs (e.g., MBCFETs) at 3nm and below. Complex 3D structures.	Planar MOSFETs (at 28nm), early FinFETs (at 16/14/12nm). Simpler structures.
Lithography & Patterning	EUV (Extreme Ultraviolet) lithography for critical layers is essential. Multi-patterning (e.g., SAQP) for some DUV layers if EUV not fully deployed. Extremely complex and restrictive design rules.	Primarily DUV (Deep Ultraviolet) immersion lithography. Double patterning (DPT) common for critical layers. Simpler design rules.
Parasitics (RC)	Interconnect Resistance (R) and Via Resistance are highly dominant over Capacitance (C). Significant impact on wire delay and IR drop. Higher variability in parasitics. Coupling capacitance (Cc) is still a major concern.	Capacitance (C) was often more dominant in interconnect delay compared to Resistance (R).
Variability (PVT, OCV)	Very high impact of process variations (Random Dopant Fluctuations - RDF, Line Edge Roughness - LER, Work Function Variation). Statistical timing (e.g., POCV) and variation-aware design are mandatory.	Lower relative impact of process variations. Deterministic timing models (OCV, AOCV) were more commonly sufficient.
Operating Voltage (Vdd)	Significantly lower (e.g., < 0.8V, approaching 0.5-0.7V). Smaller noise margins.	Higher (e.g., ~0.9V to 1.V+). Larger noise margins.
Leakage Current	Higher relative leakage current due to smaller device dimensions and lower Vt. Complex leakage control mechanisms are vital.	Lower relative leakage current.
Power Density & Thermal	Much higher transistor density leads to significantly increased power density and severe thermal hotspots. Thermal management is a critical design constraint.	Lower power density, thermal issues generally more manageable.
Design Rules & DFM	Extremely complex, numerous, and restrictive design rules. Extensive Design for Manufacturability (DFM), Design for Yield (DFY), and Design for Reliability (DFR) checks are mandatory. Litho hotspots, CMP effects, stress effects are major concerns.	More relaxed design rules. DFM was important but less acutely critical.
Interconnect Materials	Exploration/use of new materials like Cobalt (Co), Ruthenium (Ru) for liners, vias, or even wires to combat high resistance of Cu at very small dimensions.	Predominantly Copper (Cu) interconnects with traditional barrier/liner materials (e.g., Tantalum, Titanium).
IR Drop & Electromigration (EM)	More severe due to lower Vdd, higher wire R, and higher current densities. Requires very robust power distribution network (PDN) design.	Less severe compared to lower nodes.
Cost (Design & Manufacturing)	Exponentially higher NRE (Non-Recurring Engineering) costs (masks, IP), more complex manufacturing processes, and longer design cycles.	More mature processes with lower NRE costs.
Design Complexity	Significantly higher, requiring more sophisticated EDA tools, advanced modeling, and larger design teams.	High, but less complex than cutting-edge nodes.
Standard Cell Height	Smaller (e.g., 6-track, 5-track, or even lower). Tighter pin access.	Larger (e.g., 9-track, 10-track, 12-track). Easier pin access.

7nm Fab Challenges: https://semiengineering.com/7nm-fab-challenges/
Signoff Challenges at Advanced Nodes: https://www.einfochips.com/blog/sign-off-the-chip-asic-design-challenges-and-solutions-at-cutting-edge-technology/

What are the different types of placement bounds/blockages?

Wed, 20 Aug 2025 00:00:00 +0000

o Placement blockage of type “Hard” means that placeDesign will not place any cells in this area. Use this blockage type to totally restrict standard cells from being placed here.

A placement blockage of type “Soft” means that placeDesign will not place any cells in this region. However, placement legalization, timing optimization, and clock tree synthesis (CTS) can place buffers/inverters in this area. This blockage type is often used to block channels between macros. It prevents the placer from placing standard cells in this area, thus avoiding congestion problems. However, optimization is allowed to insert buffers/inverters in these channels, which is useful when buffering long nets and can improve timing and routability.

What challenges in power planning for 7nm and advanced nodes?

Wed, 20 Aug 2025 00:00:00 +0000

oIncreased Resistance: Interconnect wires become thinner and taller (to try and mitigate R increase, but R still dominates over C). Via resistance also increases dramatically. This makes the power grid inherently more resistive, leading to higher IR drop (V=I×R).

Lower Supply Voltage (Vdd): Operating voltages are significantly lower (e.g., < 0.8V). This means the allowable noise margin for IR drop (both static and dynamic) is much smaller (e.g., 5-10% of Vdd is a smaller absolute voltage). Designs become extremely sensitive to voltage variations.
Higher Current Density: While voltage decreases, the density of transistors increases significantly, leading to higher overall current density (J) in the power grid, especially localized hotspots. Risk of EM.
Dynamic IR Drop (Voltage Droop): Faster switching speeds and higher localized current demands exacerbate dynamic voltage droop. Providing sufficient instantaneous current through the high-resistance grid requires a very dense decap cell strategy and a robust PDN.
Complexity of PDN Design: Achieving the required low resistance and meeting IR/EM targets often necessitates using more metal layers for the power grid, wider straps, and significantly more vias, consuming valuable routing resources needed for signals. Balancing power needs with signal routability becomes harder.

7nm Challenges (includes power/interconnect): https://www.wipro.com/blogs/mohit-bansal/the-benefits-and-challenges-of-7nm-technology/

What does max transition and max capacitance mean? Which one is given priority and why?

Wed, 20 Aug 2025 00:00:00 +0000

o Max Transition (or Max Slew): This is a design rule constraint specified in the library (.lib) that defines the longest permissible time for a signal to transition from one logic level to another (e.g., 10% to 90% of Vdd).

Purpose: Ensures signal integrity and predictable cell behavior. Slow transitions can cause:

Increased sensitivity to noise (crosstalk).

Increased short-circuit power consumption within the receiving cell.

Unreliable timing (cell delays are characterized based on input slew; very slow slews might fall outside characterization).

What is the content inside an SDC file? How is the clock defined? Why is delay defined on IO ports?

Wed, 20 Aug 2025 00:00:00 +0000

oSDC Version: Specifies the SDC standard version used (e.g., set sdc_version 2.1).

Units: Defines units for time, capacitance, resistance, voltage, current, power (e.g., set_units -time ns …).

Clock Definitions:

create_clock: Defines primary clocks entering the design (at ports or internal pins), specifying their source, period, waveform (duty cycle, edge times).

create_generated_clock: Defines clocks generated internally (e.g., by PLLs, clock dividers/multipliers) based on a master clock.

set_clock_groups: Defines relationships between clocks (synchronous, asynchronous, exclusive).

What is the difference between std. cell LEF and tech LEF? What content is in tech LEF?

Wed, 20 Aug 2025 00:00:00 +0000

o Technology LEF (tech.lef): Defines the process technology rules and properties. It contains information common to the entire chip manufacturing process, independent of specific standard cells.

Content:

Layers: Defines all routing (metal), cut (via), masterslice (poly, diffusion), and other layers used in the technology. Includes name, type, direction preference, pitch, width, spacing rules (DRCs), resistance, capacitance per unit area/length, thickness, color (for multi-patterning).

Vias: Defines standard via types connecting different layers, including their cut patterns, enclosure rules, and resistance.

What is your Reg2Reg WNS/TNS in the final netlist? What if it's extremely high? What about ICG WNS?

Wed, 20 Aug 2025 00:00:00 +0000

oReg2Reg WNS/TNS:

Acceptable: A small negative WNS (e.g., -50ps to -200ps for a multi-GHz design, perhaps -10% to -20% of the clock period) might be considered acceptable as a starting point for PnR. TNS should ideally be manageable.

Context: The acceptable value depends on how much improvement is expected from PnR optimizations (better placement, buffering, useful skew, more accurate parasitics).

Extremely High Negative WNS/TNS: If the WNS is very large negative (e.g., approaching or exceeding the clock period) or TNS is enormous:

Unrealistic Constraints: Clock frequency target is too high for the technology/architecture. SDC constraints (I/O delays, exceptions) might be incorrect or too tight.

What sanity checks are performed before starting floorplan / after receiving the synthesized netlist?

Wed, 20 Aug 2025 00:00:00 +0000

oNetlist Checks:

o Syntactic Correctness: Ensure the Verilog netlist format is correct and parsable by the PnR tool.

o Logical Equivalence Check (LEC): Formally verify that the synthesized netlist is logically equivalent to the golden RTL

o Connectivity Issues:

§ Floating Inputs: No gate input pins should be left unconnected (floating)

§ Multi-Driven Nets: Check for nets driven by more than one output

§ Unloaded Nets/Outputs: Outputs driving no load might indicate redundant logic or connectivity errors.

What utilization do you target at the start? Considering a design with 70% vs 50% utilization, which would you take?

Wed, 20 Aug 2025 00:00:00 +0000

o Target Utilization at Start: The initial target core utilization for PnR typically ranges from 50% to 70%.

Lower utilization (e.g., 50-60%) provides more whitespace, making routing easier, reducing congestion, potentially improving timing (less detour), and offering more flexibility for CTS and ECOs. This is often preferred for high-performance designs or designs with known congestion challenges.

Higher utilization (e.g., 65-70%, sometimes even higher for specific blocks) aims to minimize die area (cost). However, it increases the risk of congestion, may make timing closure harder, and leaves less room for post-route optimizations and ECOs.

Which state (switching or not switching) consumes more power? Which VT leaks more (HVT vs LVT)?

Wed, 20 Aug 2025 00:00:00 +0000

oSwitching State: The switching state consumes significantly more power in CMOS circuits. This is called dynamic power and has two main components:

Switching Power: Charging and discharging load capacitances (Psw=αCVdd2f, where α is activity factor, C is load capacitance, Vdd is supply voltage, f is frequency).

Short-Circuit Power: For a brief moment during switching, both PMOS and NMOS transistors can be partially ON, creating a direct path from VDD to VSS.

Why build voltage islands? What are the requirements for low power design?

Wed, 20 Aug 2025 00:00:00 +0000

oVoltage islands (or power domains operating at different voltage levels) are created primarily to reduce overall power consumption (both dynamic and static).

Dynamic Power Reduction: Pdynamic∝Vdd2. By operating non-performance-critical blocks (islands) at a lower supply voltage (e.g., 0.7V) compared to performance-critical blocks (e.g., 0.9V), the dynamic power consumption of the low-voltage blocks is significantly reduced.

Static Power Reduction: Pstatic∝Vdd×Ileakage. Lowering Vdd directly reduces static power. Additionally, leakage current (Ileakage) itself often decreases at lower voltages.

What is the difference between OCV, AOCV, and POCV? Why POCV?

Tue, 19 Aug 2025 00:00:00 +0000

Sources of Variation: The primary sources of variation that necessitate derates are:

·PVT (Process, Voltage, Temperature) Variations: These are inter-chip variations.

o Process: Variations in manufacturing (e.g., lithography wavelength, defects) can alter transistor parameters like oxide thickness, dopant levels, and physical dimensions (W/L), which in turn affect threshold voltage (Vt) and current (I), and thus cell delay. Dies at the center of a wafer are more accurate than those at the periphery.