- oNetlist Checks:
o Syntactic Correctness: Ensure the Verilog netlist format is correct and parsable by the PnR tool.
o Logical Equivalence Check (LEC): Formally verify that the synthesized netlist is logically equivalent to the golden RTL
o Connectivity Issues:
§ Floating Inputs: No gate input pins should be left unconnected (floating)
§ Multi-Driven Nets: Check for nets driven by more than one output
§ Unloaded Nets/Outputs: Outputs driving no load might indicate redundant logic or connectivity errors.
§ Combinational Loops: Check for unintended feedback loops in combinational logic.
- oDesign Structure:
o Empty Modules/Black Boxes: Identify any modules referenced in the netlist but lacking a definition (black boxes) or empty modules. Ensure these are expected (e.g., hard macros, analog blocks) and corresponding models/LEF exist.
o Unresolved References: Similar to black boxes, ensure all cell instantiations have corresponding definitions in the libraries.
o Assign Statements: Netlists should generally not contain continuous assignment (assign) statements; these should be synthesized into gates.
- oConstraints Checks (SDC - Synopsys Design Constraints):
o Clock Definitions: Ensure all clocks are defined (create_clock, create_generated_clock) and reach all sequential elements (no unclocked registers).
o I/O Delays: Check if input (set_input_delay) and output (set_output_delay) delays are defined for all primary I/O ports involved in timing paths.
o DRC Constraints: Verify that design rule constraints like set_max_transition, set_max_capacitance, set_max_fanout are appropriately defined.
o Unconstrained Paths/Endpoints: Identify any timing paths or endpoints that are not covered by existing constraints (using check_timing). These might need explicit constraints or could be intended false paths.
o Multi-Driven Clocks: Check for registers driven by multiple clocks, which usually indicates an error in the SDC or design.
- oPower Intent Checks (UPF/CPF)
o Netlist Qualification: https://www.design-reuse.com/articles/52476/synthesis-methodology-netlist-qualification.html