- Power Grid Integrity: Due to lower Vdd and higher current density, the power grid must be extremely robust. This means more metal layers allocated for power
- Pin Placement Complexity: Higher pin counts and tighter bump pitches make I/O pin placement challenging.
- Increased Pin Density & Access: Macros at 7nm often have extremely high pin densities. This requires wider channels, careful orientation and blockages.
- Complex DRCs:
- Timing Impact: Due to high wire resistance
Physical Design Interview Guide
The Ultimate Guide to Physical Design Interview Questions