Different CTS types? What are benefits of those?

1. Conventional / Single Point CTS

This is the standard approach used for lower-frequency designs with fewer “sinks” (flip-flops/registers).

• Structure: It has a single clock source that distributes the signal to every corner of the design. The “point of divergence” (where the paths split) is right at the clock source.
• Benefits:
  • High Power Efficiency: Because clock gating is typically done near the source, large sections of the tree can be shut off, saving significant dynamic power.
  • Simplicity: It is the easiest to implement using standard EDA tool flows.
• Trade-offs: * OCV Sensitivity: Because the clock paths are largely “uncommon” (they don’t share much of the same wire/buffer path), manufacturing variations (OCV) affect each branch differently, leading to higher skew.
  • High Insertion Delay: The signal has to travel through many levels of buffers to reach the entire chip.

2. Clock Mesh Structure

This is the most robust structure, creating a dense grid of shorted wires driven by “mesh drivers.”

• Structure: A network of pre-mesh drivers brings the signal to a massive metal mesh (horizontal and vertical stripes). The registers then tap into this mesh using very short local connections (only 2-3 stages).
• Benefits:
  • Ultra-Low Skew: The mesh “smooths out” arrival time differences because the drivers are all shorted together.
  • OCV Tolerance: Since the paths are highly common and the local trees are very short, On-Chip Variation has a minimal impact.
  • Low Insertion Delay: The signal reaches the registers much faster than in a traditional tree.
• Trade-offs:
  • High Power: The mesh is always switching, and clock gating can only be done at the very end (local level).
  • Resource Heavy: It requires significant metal routing resources and is complex to implement.

3. Multi-Source CTS (The Hybrid)

This acts as a middle ground between a simple tree and a full mesh.

• Structure: It uses a “global distribution” (often a sparse mesh or an H-Tree) to deliver the clock to specific “tap points” across the chip. From these points, small local clock trees take over to reach the sequential cells.
• Benefits:
  • Optimized Performance: It offers less insertion delay and lower skew than a conventional tree without the massive power penalty of a full mesh.
  • Moderate OCV Impact: By sharing a common global distribution path, it reduces the susceptibility to variation compared to a single-point tree.
• Comparison: It is considered “moderate” across almost every design metric—power, performance, and area.