1. Clock Tree Reports:
Skew Report: Verify that the achieved maximum skew (global and potentially per skew group) meets the target specified in the CTS spec/constraints.
Latency Report: Check the minimum and maximum insertion delays. Ensure they are within acceptable ranges or meet specific targets.
DRC Report (CTS Specific): Check for violations of max_transition, max_capacitance, max_fanout specifically on the clock tree buffers/inverters and nets.
Duty Cycle and MPW violatons.
Clock tree power.
SI and cross talk.
Timing Analysis (Post-CTS STA):
Placement Legality: Verify that the newly inserted clock tree buffers/inverters are legally placed (checkPlace, checkLegality). Sometimes aggressive placement during CTS can cause overlaps.
Congestion: The addition of clock buffers and the routing of clock nets (even if only estimated by trial route) can significantly increase congestion
Clock Tree Structure Verification: and cts exceptions are proper.
Utilization/Area: Check the increase in cell count and utilization due to the added clock tree cells.
Log Files: Review tool log files for any critical warnings or errors generated during the CTS process.
Checks After CTS: https://fr.scribd.com/presentation/637490970/Untitled