Minimize Clock Skew
Meet Insertion Delay Targets
Achieve Target Transition Times (Slew): Ensure the clock signal edges are sharp (fast transitions) throughout the network to guarantee reliable clocking of sequential elements and minimize sensitivity to noise. Meet max_transition DRC constraints.
Too tight trans causes more bufs/inv and increases area, power and latency.
Loose trans can cause more leakage, sensitive to noise and increased delay.
Meet Other DRCs: like max_capacitance and max_fanout
Minimize Power Consumption: Build the clock tree with optimum power possible.
Maintain Signal Integrity and Routability:
No timing violations.