o Conventional CTS (Buffer/Inverter Tree): The most common approach. The tool starts from the sinks and works backward or starts from the root and works forward, clustering nearby sinks, inserting buffers/inverters to meet skew, latency, and DRC targets, and progressively building a tree structure. The exact topology isn’t strictly predefined but emerges based on sink locations and optimization goals. Modern tools use sophisticated algorithms (e.g., clock concurrent optimization - CCOpt) that optimize the clock tree and logic paths concurrently.
H-Tree:
Pros: Theoretically provides perfect zero skew if sinks are perfectly distributed and loads are balanced. Good for regular structures.
Cons: Impractical for real designs where sinks are unevenly distributed, blockages exist, and loads vary. Consumes significant routing resources and can have high insertion delay. Pure H-trees are rarely used; however, H-tree topology might be used for the top levels of the clock tree driving major branches.
X-Tree: Similar to H-Tree but uses diagonal connections. Less practical due to non-Manhattan routing challenges.
Mesh: A grid of interconnected clock lines driven by multiple drivers, typically used for very high-performance designs. Sinks tap off the nearest mesh segment. Provides very low skew and OCV robustness but consumes high power and routing resources.
Multi-Source CTS (MSCTS): Used when multiple clock sources drive different parts of the tree; requires careful balancing between sources.
Types of Cells Used:
Clock Buffers/Inverters: Libraries often contain cells specifically designed for clock trees (“clock buffers/inverters”). These typically have:
Balanced Rise/Fall Delays: Critical for minimizing duty cycle distortion.
Higher Drive Strength: To drive large fanouts common in clock trees.
Lower Delay Variation: More robust against PVT variations.
VT Mix (Threshold Voltage): Clock tree cells are usually chosen from lower Vt variants (LVT).
Reason: Faster low-Vt cells help minimize insertion delay. They have higher leakage but the performance benefit on the critical clock network often outweighs the leakage penalty.
Another reason is it has less delay variation and less OCV impact.
H-Tree Pros/Cons: https://vorasaumil.wixsite.com/pdinsight/post/clock-tree-synthesis-part-3-clock-structures-its-implementation-and-analysing-the-results
Buffers vs Inverters: http://vlsi-soc.blogspot.com/2014/12/inverter-vs-buffer-based-clock-tree.html