o Clock Skew: The difference in arrival time of the clock at capture FF and launch FF.
Local Skew: Skew between two specific, related flops (e.g., launch and capture flop of a timing path).
Global Skew: The difference between the maximum and minimum clock latency across all sinks in a domain.
Causes of Skew:
Different Path Lengths: The physical distance (wire length) from the clock root to different sinks varies due to their placement locations.
Different Path Delays: Even with equal lengths, paths can have different RC delays due to different routing layers, widths, or nearby coupling nets.
Buffer/Inverter Variations: Differences in buffer/inverter delays due to placement, drive strength variations, VT variations, or different loading conditions (fanout).
Uneven Loading: Branches of the clock tree driving significantly different capacitive loads can experience different delays.
On-Chip Variation (OCV): Process, voltage, and temperature variations across the die cause cells and wires in different paths to have slightly different delays.
Useful skew option used to help setup violations.
Resolving/Balancing Skew (CTS Process):
Buffer/Inverter Insertion & Sizing: The core CTS technique. The tool strategically inserts buffers/inverters and selects their drive strengths to equalize the delay down different branches of the tree. Delay might be added to faster paths to match slower paths.
Balanced Tree Topology: Algorithms aim to build a topologically balanced tree where branches have similar depths and loads.
Wire Length/Layer Adjustment: The tool tries to route clock nets to minimize length differences or uses specific layers where possible, although options are often limited by placement.
Dummy Load Insertion: Intentionally adding small capacitive loads (dummy cells) to faster paths to slow them down and match slower paths (less common now, buffer insertion is preferred).
Useful Skew (Post-CTS/Optimization): Intentionally introducing a controlled amount of skew to specific paths to help fix setup or hold violations