Clock Gating Checks: setup and hold timing checks applied to the enable signal of Integrated Clock Gating (ICG) cells.
Prevent Glitches: The primary reason is to ensure the output of the ICG cell (the gated clock) is clean and free from glitches or runt pulses. Glitches can cause flip-flops downstream to capture incorrect data or enter metastable states.
Reliable Low Power: Ensuring the checks pass guarantees the gating works reliably, achieving the intended power reduction without causing functional errors.