1. Conventional / Single Point CTS

This is the standard approach used for lower-frequency designs with fewer “sinks” (flip-flops/registers).

• Structure: It has a single clock source that distributes the signal to every corner of the design. The “point of divergence” (where the paths split) is right at the clock source.
• Benefits:
  • High Power Efficiency: Because clock gating is typically done near the source, large sections of the tree can be shut off, saving significant dynamic power.
  • Simplicity: It is the easiest to implement using standard EDA tool flows.
• Trade-offs: * OCV Sensitivity: Because the clock paths are largely “uncommon” (they don’t share much of the same wire/buffer path), manufacturing variations (OCV) affect each branch differently, leading to higher skew.
  • High Insertion Delay: The signal has to travel through many levels of buffers to reach the entire chip.

2. Clock Mesh Structure

This is the most robust structure, creating a dense grid of shorted wires driven by “mesh drivers.”

o Conventional CTS (Buffer/Inverter Tree): The most common approach. The tool starts from the sinks and works backward or starts from the root and works forward, clustering nearby sinks, inserting buffers/inverters to meet skew, latency, and DRC targets, and progressively building a tree structure. The exact topology isn’t strictly predefined but emerges based on sink locations and optimization goals. Modern tools use sophisticated algorithms (e.g., clock concurrent optimization - CCOpt) that optimize the clock tree and logic paths concurrently.

o H-Tree:

Advantages:

Zero Skew (Ideal): Theoretically capable of achieving zero skew if sinks are perfectly distributed and the tree is perfectly balanced.

Symmetric Structure: Predictable and regular routing pattern.

Disadvantages:

Impractical for Real Designs: Assumes uniform sink distribution, which rarely occurs. Blockages and routing obstacles disrupt the ideal structure.

High Insertion Delay: Can lead to long paths from the root to sinks.

Resource Intensive: Can consume significant routing area, especially on preferred layers.

• Placement Database: The design database after placement is complete, containing the locations of all standard cells (including clock sinks like flip-flops and clock gates) and macros. – it covers Timing lib. Tech lef, std cell lef, SDC etc.

CTS Specification File .ctstch**,** .cts_spec**,** This file (or equivalent tool settings) provides detailed instructions for building the clock tree:

• Target Skew: Maximum acceptable skew between sinks in the same clock domain or skew group.
• Target Max/Min Latency: Desired range for insertion delay.
• Target Max Transition: Maximum allowed transition time for clock nets.
• Buffer/Inverter List: Specifies the list of buffers and inverters the tool is allowed to use for building the tree (often restricts to specific drive strengths or balanced cells).
• DRC Constraints: Max capacitance, max fanout limits specifically for clock nets.
• NDR (Non-Default Rules): Specifies special routing rules (e.g., double width, double spacing, shielding) to be used for clock nets to improve signal integrity and reliability.
• Routing Layers: Preferred top and bottom metal layers for clock routing.
• Clock Tree Exceptions: Defines pins to be treated specially:
  • Stop/Sink Pins (Default): Normal clock endpoints to be balanced.
  • Exclude Pins: Excluded from skew/latency balancing but still receive the clock and DRV fixing (e.g., output ports, Multiplexer select pin )
  • Ignore Pins: Completely ignored by CTS balancing and DRC fixing (e.g., non-clock pins driven by clocks, test pins).
  • Float Pins: Similar to Exclude pins but allow specifying a pin delay range for balancing (used for macro models).
  • Non-stop pins: trace through the endpoints that are normally considered as endpoints of the clock tree. Ex, The clock pin of sequential cells driving generated clock are implicit non-stop pins. Clock pin of ICG.
• Skew Groups: Defines groups of sinks that should be balanced together, potentially with different skew targets than other groups.
• Clock Tree Structure Hints: May allow specifying preferred structures (e.g., H-tree for certain branches) or buffer placement constraints. Multi tap etc.

CTS Spec File Contents: https://ivlsi.com/cts-spec-file-vlsi-physical-design/

1. Clock Tree Reports:

Skew Report: Verify that the achieved maximum skew (global and potentially per skew group) meets the target specified in the CTS spec/constraints.

Latency Report: Check the minimum and maximum insertion delays. Ensure they are within acceptable ranges or meet specific targets.

DRC Report (CTS Specific): Check for violations of max_transition, max_capacitance, max_fanout specifically on the clock tree buffers/inverters and nets.

Duty Cycle and MPW violatons.

Clock tree power.

o Clock Latency (Insertion Delay): The time it takes for the clock signal to propagate from its source (the point where the clock is defined, e.g., a primary input port) to the clock pin of a specific sequential element (sink pin, e.g., a flip-flop’s CK pin).

Source Latency: Delay from the actual clock origin (e.g., crystal oscillator) to the clock definition point in the design (defined using set_clock_latency -source). This models external delay.