Physical Design Interview Guide

oIncreased Resistance: Interconnect wires become thinner and taller (to try and mitigate R increase, but R still dominates over C). Via resistance also increases dramatically. This makes the power grid inherently more resistive, leading to higher IR drop (V=I×R).

• Lower Supply Voltage (Vdd): Operating voltages are significantly lower (e.g., < 0.8V). This means the allowable noise margin for IR drop (both static and dynamic) is much smaller (e.g., 5-10% of Vdd is a smaller absolute voltage). Designs become extremely sensitive to voltage variations.
• Higher Current Density: While voltage decreases, the density of transistors increases significantly, leading to higher overall current density (J) in the power grid, especially localized hotspots. Risk of EM.
• Dynamic IR Drop (Voltage Droop): Faster switching speeds and higher localized current demands exacerbate dynamic voltage droop. Providing sufficient instantaneous current through the high-resistance grid requires a very dense decap cell strategy and a robust PDN.
• Complexity of PDN Design: Achieving the required low resistance and meeting IR/EM targets often necessitates using more metal layers for the power grid, wider straps, and significantly more vias, consuming valuable routing resources needed for signals. Balancing power needs with signal routability becomes harder.

7nm Challenges (includes power/interconnect): https://www.wipro.com/blogs/mohit-bansal/the-benefits-and-challenges-of-7nm-technology/

o Max Transition (or Max Slew): This is a design rule constraint specified in the library (.lib) that defines the longest permissible time for a signal to transition from one logic level to another (e.g., 10% to 90% of Vdd).

Purpose: Ensures signal integrity and predictable cell behavior. Slow transitions can cause:

Increased sensitivity to noise (crosstalk).

Increased short-circuit power consumption within the receiving cell.

Unreliable timing (cell delays are characterized based on input slew; very slow slews might fall outside characterization).

oSDC Version: Specifies the SDC standard version used (e.g., set sdc_version 2.1).

Units: Defines units for time, capacitance, resistance, voltage, current, power (e.g., set_units -time ns …).

Clock Definitions:

create_clock: Defines primary clocks entering the design (at ports or internal pins), specifying their source, period, waveform (duty cycle, edge times).

create_generated_clock: Defines clocks generated internally (e.g., by PLLs, clock dividers/multipliers) based on a master clock.

set_clock_groups: Defines relationships between clocks (synchronous, asynchronous, exclusive).

o Technology LEF (tech.lef): Defines the process technology rules and properties. It contains information common to the entire chip manufacturing process, independent of specific standard cells.

Content:

Layers: Defines all routing (metal), cut (via), masterslice (poly, diffusion), and other layers used in the technology. Includes name, type, direction preference, pitch, width, spacing rules (DRCs), resistance, capacitance per unit area/length, thickness, color (for multi-patterning).

Vias: Defines standard via types connecting different layers, including their cut patterns, enclosure rules, and resistance.

oReg2Reg WNS/TNS:

Acceptable: A small negative WNS (e.g., -50ps to -200ps for a multi-GHz design, perhaps -10% to -20% of the clock period) might be considered acceptable as a starting point for PnR. TNS should ideally be manageable.

Context: The acceptable value depends on how much improvement is expected from PnR optimizations (better placement, buffering, useful skew, more accurate parasitics).

• Extremely High Negative WNS/TNS: If the WNS is very large negative (e.g., approaching or exceeding the clock period) or TNS is enormous:

Unrealistic Constraints: Clock frequency target is too high for the technology/architecture. SDC constraints (I/O delays, exceptions) might be incorrect or too tight.

• oNetlist Checks:

o Syntactic Correctness: Ensure the Verilog netlist format is correct and parsable by the PnR tool.

o Logical Equivalence Check (LEC): Formally verify that the synthesized netlist is logically equivalent to the golden RTL

o Connectivity Issues:

§ Floating Inputs: No gate input pins should be left unconnected (floating)

§ Multi-Driven Nets: Check for nets driven by more than one output

§ Unloaded Nets/Outputs: Outputs driving no load might indicate redundant logic or connectivity errors.