Physical Design Interview Guide

• Primary Purpose: To prevent signal corruption from propagating from an inactive domain to an active domain.
• Isolation & Level Shifters: https://vlsitutorials.com/isolation-cells-level-shifter-cells-low-power-vlsi/

oIdeal Clock Network: During placement (pre-CTS), the PnR tool assumes an “ideal” clock network. This means:

Zero Skew: All flip-flops receive the clock edge at the exact same time.

Zero Latency (or Ideal Latency): The delay from the clock source to the flip-flops is considered zero or some idealized, non-propagated value.

• Setup time depend on clk period, skew and setup time of FF.
• Hold Time depends on skew and hold time of FF.
• Tc2q + Tcomb + Tsetup ≤ Tclk + Tskew => here even if skew is zero, dominating factor is clock period. we have reasonable values in equation to do analysis.
• Tc2q + Tcomb ≥ Thold + Tskew => skew is dominating factor in equation. here when skew is zero, data path delay just needs to be more than FF hold time. Which in many cases may always be since we don’t have exact skew yet. any hold analysis would be meaningless or highly inaccurate because the dominant factor (skew) is unknown.

Enable AOCV Mode: Set the appropriate variables/commands in the STA tool (e.g., PrimeTime, Tempus)

Specify AOCV Files: Ensure the tool points to the necessary AOCV library files (often provided as separate .aocv files or tables within the .lib).

Select Analysis Mode: Choose between ‘clock only’ or ‘clock and data’ modes. ‘Clock only’ applies AOCV derates just to clock paths for faster runtime, while ‘clock and data’ applies them to both for higher accuracy.

Sources of Variation: The primary sources of variation that necessitate derates are:

·PVT (Process, Voltage, Temperature) Variations: These are inter-chip variations.

o Process: Variations in manufacturing (e.g., lithography wavelength, defects) can alter transistor parameters like oxide thickness, dopant levels, and physical dimensions (W/L), which in turn affect threshold voltage (Vt​) and current (I), and thus cell delay. Dies at the center of a wafer are more accurate than those at the periphery.