Physical Design Interview Guide

oReg2Reg WNS/TNS:

Acceptable: A small negative WNS (e.g., -50ps to -200ps for a multi-GHz design, perhaps -10% to -20% of the clock period) might be considered acceptable as a starting point for PnR. TNS should ideally be manageable.

Context: The acceptable value depends on how much improvement is expected from PnR optimizations (better placement, buffering, useful skew, more accurate parasitics).

• Extremely High Negative WNS/TNS: If the WNS is very large negative (e.g., approaching or exceeding the clock period) or TNS is enormous:

Unrealistic Constraints: Clock frequency target is too high for the technology/architecture. SDC constraints (I/O delays, exceptions) might be incorrect or too tight.

• oNetlist Checks:

o Syntactic Correctness: Ensure the Verilog netlist format is correct and parsable by the PnR tool.

o Logical Equivalence Check (LEC): Formally verify that the synthesized netlist is logically equivalent to the golden RTL

o Connectivity Issues:

§ Floating Inputs: No gate input pins should be left unconnected (floating)

§ Multi-Driven Nets: Check for nets driven by more than one output

§ Unloaded Nets/Outputs: Outputs driving no load might indicate redundant logic or connectivity errors.

o Target Utilization at Start: The initial target core utilization for PnR typically ranges from 50% to 70%.

Lower utilization (e.g., 50-60%) provides more whitespace, making routing easier, reducing congestion, potentially improving timing (less detour), and offering more flexibility for CTS and ECOs. This is often preferred for high-performance designs or designs with known congestion challenges.

Higher utilization (e.g., 65-70%, sometimes even higher for specific blocks) aims to minimize die area (cost). However, it increases the risk of congestion, may make timing closure harder, and leaves less room for post-route optimizations and ECOs.

oSwitching State: The switching state consumes significantly more power in CMOS circuits. This is called dynamic power and has two main components:

Switching Power: Charging and discharging load capacitances (Psw​=αCVdd2​f, where α is activity factor, C is load capacitance, Vdd is supply voltage, f is frequency).

Short-Circuit Power: For a brief moment during switching, both PMOS and NMOS transistors can be partially ON, creating a direct path from VDD to VSS.

oHeader Switches: Use PMOS transistors placed between the main VDD grid (always-on supply) and the switchable VDD rail of the power domain (VDD_SW). The PMOS gate is controlled by the sleep/enable signal. When OFF (sleep signal asserted), they disconnect the domain from VDD.

• Footer Switches: Use NMOS transistors placed between the switchable VSS rail (VSS_SW) of the power domain and the main VSS grid (always-on ground). The NMOS gate is controlled by the sleep/enable signal. When OFF, they disconnect the domain from VSS.
• Combined Header/Footer: Some designs might use both header and footer switches for more robust power cut-off, although this adds complexity and area.

oVoltage islands (or power domains operating at different voltage levels) are created primarily to reduce overall power consumption (both dynamic and static).

Dynamic Power Reduction: Pdynamic​∝Vdd2​. By operating non-performance-critical blocks (islands) at a lower supply voltage (e.g., 0.7V) compared to performance-critical blocks (e.g., 0.9V), the dynamic power consumption of the low-voltage blocks is significantly reduced.

Static Power Reduction: Pstatic​∝Vdd​×Ileakage​. Lowering Vdd directly reduces static power. Additionally, leakage current (Ileakage​) itself often decreases at lower voltages.