Physical Design Interview Guide

oCongestion Maps: Use the PnR tool’s GUI to visualize the congestion map generated after trial/global routing. Identify hotspots (high overflow areas, usually color-coded red/orange). Check both horizontal and vertical layer congestion.

• reportCongestion - list the most congested regions.

Reasons could be - High Cell Density - Macro Pin Areas - Narrow Channels - Bad Floorplan - Specific Logic: Are certain types of logic (e.g., large muxes, data path logic) concentrating connections in one area?

oUsually iterative to find best value for padding but can be generalise like,

• If local congestion in one module, depending on congestion %, we can increase.
• If cells has high pin density, padding required might be more.

• Logical Grouping (UPF create_power_domain -elements**):** All instances specified as elements of a power domain ideally need to be placed together physically.
• Area Estimation: Estimate the total area required for all the standard cells and macros belonging to the power domain. Add margin for internal routing, CTS buffers, and special cells (power switches, isolation cells often placed at the boundary).
• Power Grid Considerations: The voltage area needs its own internal power grid distribution (stripes/rails) connected appropriately to either the global grid (for always-on domains) or through power switches (for switchable domains). The size and shape must accommodate this grid.
• Based on above factors and required utilization of voltage area, we can determine domain area.
• The voltage area (create_voltage_area): Associate the physical area with the logical power domain name from UPF. Use placement guidance features (regions, fences) to enforce that cells belonging to the domain are placed within the defined voltage area.

If height is more, block has longer vertical tracks but less in number. Block has more number of horizontal tracks available. Chances are there will be higher congestion on vertical tracks. So place pins and macros such that it utilises more number of horizontal tracks.

oAnalyze Connectivity (Flylines) – all fanin, all_fanout.

• Use trace macro feature of Innovus.

Group by Hierarchy/Connectivity

Consider Data Flow:

Periphery Placement: Generally place macros around the edges of the core area, leaving the central area for standard cells. This simplifies power delivery to macros and avoids blocking standard cell placement/routing in the core center.

Pin Accessibility: Orient macros so their pins face towards the core logic they connect to, minimizing wire length and routing complexity.

o Identify the Bottleneck: Determine why the hotspot exists even with uniform density targets. Is it due to:

Macro pin congestion?

A narrow channel between macros/blockages?

A concentration of high-pin-count cells?

Specific routing patterns forced by the logic structure?

• partial placement blockages or density screens specifically over the hotspot GCells. This forces lower density only where needed, rather than globally.
• Macro/Blockage Adjustments:

Cell Padding: Apply cell padding specifically to cells within the congested region, or to specific cell types causing the issue there.