Physical Design Interview Guide

oPnR Target: The target set in the PnR tool (e.g., via SDC set_max_transition command) is usually a fraction of the library limit, often around 70-80% of Lib_Max_Trans.

• Provides design margin. Gives the PnR tool more headroom to work with. Helps improve correlation between PnR timing estimates and signoff STA results, which use more accurate extraction and timing models. Tighter transition control generally improves noise immunity.

Decision Process: The exact percentage or value is often project-specific or methodology-defined, based on:

oRequirement Analysis: Understand the power consumption estimate of the design (static and dynamic), voltage levels required, number of power domains, IR drop targets, and EM limits.

• Define Structure: Design the hierarchy of the PDN, typically involving:
• Power Pads/Bumps
• Power Rings
• Power Stripes:
• Power Rails

Calculate Widths/Spacing: Determine the required width and spacing of rings and stripes based on current density requirements

Layer Assignment: Assign specific metal layers for rings, horizontal stripes, and vertical stripes.

Cell Sizing, VT Swap to allowed VT at placement, Buffer insertion, Logic optimization, These optimizations are typically performed automatically by the place_opt / optDesign -preCTS commands based on the timing constraints (SDC) and available libraries and don’t use settings.

• Need manual observation of critical paths,
• high fanout: it can cause trouble in closing timing as balancing CTS and placing all FFs properly will be difficult for the tool.
• Cells are spread for longer distance: check the connectivity of start point endpoint, analyse module connection and give appropriate bound or region.
• Macro placement analysis and fanin fanout checks gives better idea.

o Minimize wire length between pins and the internal logic/macros they connect to.

Reduce routing congestion, especially near the block boundary.

Align pins logically with connected blocks at the next level of hierarchy.

Meet timing requirements for critical interface paths.

Ensure routability and avoid pin access issues.

Group related signals (e.g., buses) together logically.

• Understand Connectivity: Analyze which internal blocks/macros connect to which I/O pins (using flylines or schematics). Understand connectivity to external blocks at the top level.
• Consider Top-Level Context: If the block is part of a larger design, align pin locations with the corresponding connections on adjacent blocks or routing channels at the top level to minimize top-level routing detours.
• Tool Assistance: PnR tools provide features for pin placement:

Automatic placement based on connectivity (“snap pins” or similar).

Configure the tool to find the required library files (.lib, .lef).

• Innovus:
• ICC2: set_app_var search_path ./libs ; set_app_var target_library {slow.db} ; set_app_var link_library “* slow.db” (Specify LEF via read_tech_lef, read_cell_lef or read_ndm)
• Load Physical Libraries (.lef**):** Read the technology LEF and the standard cell/macro LEF files.

Innovus: Handled by init_design if paths are set, or read_lef tech.lef cells.lef

ICC2: read_tech_lef tech.lef ; read_cell_lef cells.lef (or read_ndm for NDM libraries which bundle lib/lef)

o Gather Inputs:

Gate Count: Number of standard logic gates from synthesis (excluding memories/macros).

Memory/Macro Area: Total area required for all hard macros, RAMs, ROMs, IP blocks (obtained from their datasheets or abstracts).

IO Count: Number of Input/Output pads/bumps required.

Technology Information: Gate density (gates/mm²) for the target standard cell library, standard cell height, required IO pad dimensions/pitch.

Target Utilization: The desired percentage of the core area that will be occupied by standard cells and macros after placement.