Physical Design Interview Guide

o Clock Skew: The difference in arrival time of the clock at capture FF and launch FF.

Local Skew: Skew between two specific, related flops (e.g., launch and capture flop of a timing path).

Global Skew: The difference between the maximum and minimum clock latency across all sinks in a domain.

Causes of Skew:

Different Path Lengths: The physical distance (wire length) from the clock root to different sinks varies due to their placement locations.

oIf you place ICG near to source, dynamic power consumption will reduce. This is because most of the clock buffers are in fanout of clock gater. These clock buffers will not toggle when clock gating is enabled.

• But placing ICG near to source increases the uncommon paths. These uncommon paths can behave differently, so during STA these need to be taken into account that extra uncertainty.
• If you place ICG near to sink, most of the clock buffers are in common path. It is easy to met timing compared to scenario-1.
• But at the same time dynamic power consumption is increased.
• Remember, there is trade-off between power and timing.
• Ideally, Integrated Clock Gating (ICG) cells should be placed physically close to the group of flip-flops (sinks) they are gating.

Improve CTS Balancing: CTS tools balance delay up to the inputs of the ICG cells. Placing the ICG close to the sinks means the final, unbuffered gated clock segment is short and contributes less variable delay, making overall skew balancing more predictable.

oDefining Modes: Different operating modes are : Functional mode - FUNC and test Modes: Scan Shift, Scan Capture, BIST

• Defined in MCMM setup with create_constraint_mode command and given separate SDC of each mode.
• Separate SDC Files: Each SDC file contains the appropriate set_case_analysis settings, relevant clock definitions (test clocks might differ from functional clocks), and potentially different timing exceptions or I/O delays specific to that mode.
• Mode-Specific Constraints within one SDC: Less commonly, complex logic within a single SDC file might be used to apply constraints conditionally, but separate SDCs or set_case_analysis are standard.

Checking Simultaneously (MMMC):

o We need to reduce cell delay or Net delay or use more skew – can use various methods for each.

• o Reduce Cell Delay:

• oCell Sizing (Upsizing): Increase drive strength of cells on the critical path. (Effective for small to moderate violations).

• oVT Swapping (Lowering Vt): Swap cells to faster, lower-Vt variants (HVT->SVT->LVT). (Effective, but increases leakage).

• oReduce amount of buffering if excessive bufs are added.

• o Reduce Net Delay:

oPath Summary:

Startpoint: Where the path begins (input port or flop clock pin).

Endpoint: Where the path ends (output port or flop data input pin).

Path Group:

Path Type: Setup, Hold, Recovery, Removal, Min Pulse Width, etc.

Slack:

Data Arrival Time Path: Details the delay contribution of each element along the data path:

Clock Network Delay (Launch): Latency from clock source to launch flop clock pin (relevant post-CTS).

Clock-to-Q Delay: Delay through the launch flop.

oNO. Even if setup and hold timing checks pass, significant Design Rule Violations (DRVs) either on data or clock needs to be fixed.

Reliability: Slow transitions (max_transition violation) make sequential elements susceptible to noise, glitches, and potential metastability

Timing Accuracy: buffers/inverters are characterized based on expected input transitions and output loads. Violating max_transition or max_capacitance means the library timing models used for setup/hold analysis are inaccurate, invalidating the “clean” timing result. The actual delays might be worse.