Physical Design Interview Guide

If macros having pins in middle or side with no pins can be abutted if technology allows.

o Filler Replacement: Tools often place decaps in available whitespace within standard cell rows, replacing filler cells. This is the most common method.

Near High-Switching Logic: Targeted placement near blocks or cells known to have high switching activity (e.g., clock buffers, data path muxes, bus drivers).

Around Macros: Placing decap cells in the channel space surrounding memory macros or other large IP blocks.

Under Power Straps: Some flows allow placing decap cells directly underneath higher-level power grid straps.

Cell Sizing / (Downsizing): Replace cells on non-critical timing paths with smaller drive-strength variants (e.g., X4 -> X2 -> X1).

Removing unnecessary buf/inverters: If added on short nets, may not be really required and can be deleted.

Leakage Optimization Modes: PnR/Optimization tools often have specific modes or commands (setOptMode -powerEffort high, optimize_power)

Clock Gating Enhancement: While primarily done during synthesis/CTS, post-route optimization might identify further opportunities for clock gating refinements or sizing of clock gating cells themselves, assuming it doesn’t impact timing.

Scripting: Tcl scripts can be written to trace paths between registers (e.g., using all_fanin/all_fanout recursively or dedicated path tracing commands) and count the number of combinational cells encountered.

o Creating a Voltage Area (Physical Implementation): A voltage area is a physical region on the chip floorplan designated to contain logic operating at a specific voltage level different from other regions, or logic that can be power-gated:

Define the physical boundary (coordinates) of the region- create_voltage_area

Associate this region with a specific power domain defined in the UPF/CPF.

cells belonging to the corresponding power domain are placed within this physical voltage area during placement.

oClean Sanity Checks: The netlist must pass all critical sanity checks:

No fatal errors in check_design / check_netlist (no multi-driven nets, no floating inputs on critical paths, correct connectivity).

No unresolved references (check_library passes, all cells have lib/lef).

No critical errors in check_timing (all clocks defined, critical paths constrained, no unconstrained registers intended to be clocked). Minor unconstrained paths might be acceptable if understood and deemed non-critical or intended false paths.