Physical Design Interview Guide

• CTS tools on global skew to start implementing clock tree. The idea is that minimizing the global skew will automatically minimize the local skew as global skew is the upper bound of local skew.
• Global skew balancing attempts to make the propagated clock timing match the ideal mode clock timing by balancing the insertion delay (clock latency) between all sinks.
• If you are working on a block and it is a full chip clock domain, the global skew will make effect at full chip timing for global clock balance. You need to meet the latency &. skew requirements for chip timing close.

oTSV (Through-Silicon Via): A vertical electrical connection (via) that passes completely through a silicon wafer or die. Used in 3DIC or 2.5D Chips, allowing different dies to be stacked vertically and interconnected directly using TSV and bumps.

• Physical Definition (LEF): A TSV would be defined in a manner similar to a standard via but with unique properties:
• Layer Type defined as “TSV” so tool understands it is not normal cut layer.
• It would have specific landing and covering layers (top and bottom metals it connects to).
• Dimensions (diameter, pitch).
• TSV-to-TSV or other metal spacing rules

oMulti-Patterning Rules: Assigning diff masks to shapes based on adjacent mask, if it is odd cycle violation, loop violation.

• Via Rules:
• Via Stacking & Alignment: Very tight rules on stacking multiple vias and their alignment to metal layers above and below.
• Via Enclosure by Metal: Stricter metal enclosure around vias.
• Interconnect Rules:
• Minimum Metal Pitch: Extremely tight metal width and spacing rules.
• End-of-Line (EOL) Spacing: Specific, often larger, spacing required at the ends of metal lines.
• Complex Conditional Spacing: Spacing rules that change based on parallel run length, adjacent feature types, or layer.
• fixing-double-patterning-errors-at-20nm

VT Types: Lower Vt has less delay variation across corners compared to higher vt

Cell Types: delay buffers and complex cells has higher variation compared to normal buf/inverter.

oA “cell cannot be legalized” error during an ECO (especially a hold ECO, which often involves adding buffers) means the PnR tool cannot find a valid, DRC-clean placement location for the newly added or modified cells that aligns with the site rows and doesn’t overlap with other cells.

High Cell Density/Congestion: There’s simply no physical space (empty sites) to place the new buffer without causing overlaps.

Filler cells not removed from the design.

oStatic IR drop analysis aims to determine the **average, steady-state voltage drop** across the power grid.

• the baseline voltage level experienced by cells over a longer period, primarily influenced by leakage and the average rate of switching.

• Average current calculated from average leakage and average switching power provides a measure of the continuous load on the power grid.

• In some low-activity modes or technologies with high leakage, the average leakage current can be a significant contributor to the overall static power consumption and thus the static IR drop.