Physical Design Interview Guide

oHigh Leakage from Antenna Cells: Antenna cells typically contain protection diodes connected to the input pins. These diodes, even when reverse-biased during normal operation, contribute a small amount of junction leakage current. If many antenna cells are added throughout the design, this cumulative leakage can become significant, especially in low-power designs.

• Use jogging to upper layer: If resources available, can be routed to upper layer to reduce antenna effect on lower layer. Routing on upper layer may or may not cause new antenna violations depending on what is cumulative metal area of upper layer.
• Floating Cell Addition for Antenna Fixing? Adding a floating cell, with input connected to gate with antenna violation and output floating can help in antenna violation by increasing gate area.
• This can increase the load on the net and may impact the timing.

o Functional ECOs generally take precedence over DFT ECOs if the bug impacts core functionality. For scan ECO, test coverage target need to be checked, if without scan ECO, test coverage is below required target, it is must and other options must be evaluated.

oIn a low-power project with specific operating performance points (OPPs) like:

• “low_svs” (Low Standard Voltage Swing, likely a power-saving mode)
• “turbo” (a high-performance mode, likely at a higher voltage),

Setup Analysis:

low_svs Mode: Analyze setup at the slowest process corner (SS/SSG) combined with VddL and worst-case temperature (often high temp for CMOS). This is SSG_VddL_HighTemp_RCworst. This represents the slowest the logic will be in low power mode.

turbo Mode: Analyze setup at the slowest process corner (SS/SSG) combined with VddH and worst-case temperature. This is SSG_VddH_HighTemp_RCworst. This is the absolute performance bottleneck.

oPhysical Design Database (DEF): Contains the placed locations of all cells and the layout of the power grid

Parasitic Resistance (RC Extraction or SPEF): Accurate resistance values for all segments of the PDN (metal wires and vias). This usually comes from an RC extraction tool run on the power grid layout (e.g., from Quantus/StarRC). Sometimes derived from LEF/tech files for early estimates.

Library Power Information (.lib**):** Specifies the average leakage power (or current) consumed by each standard cell and macro.

o Vector-based Analysis: Used VCD (Value Change Dump) or FSDB files generated from gate-level simulations of specific, high-activity scenarios (e.g., boot-up sequence, high-performance benchmark execution, specific test modes). These vectors provide accurate, cycle-by-cycle switching activity for those specific scenarios, allowing us to identify peak IR drop and EM stress under known critical operating conditions

• Vectorless Analysis: To ensure broader coverage and identify potential worst-case scenarios not easily captured by specific VCDs, used vectorless dynamic analysis.
• Usually Vectorless is often used earlier in the flow for faster feedback, while vector-based analysis with critical scenarios mandatory for final signoff
• Given Toggle Rate? à Yes, toggle rates were used, primarily for:
• Static IR Drop/Power Analysis: Average toggle rates (often derived from synthesis estimates, statistical propagation, or averaged from simulations) used along with leakage data to calculate the average current for static analysis.
• Vectorless Dynamic Analysis (Seeding): Some vectorless techniques might use initial toggle rate information as a starting point for activity propagation or statistical analysis.
• Given TWF file? Yes, TWF (Timing Window File) files were used as input for dynamic analysis, especially for vectorless methods
• A TWF file contains information about the possible switching time windows for signals in the design.
• For each net or pin, it specifies the earliest and latest possible time (relative to the clock edge) that a signal transition (rise or fall) can occur

oDRC (Design Rule Check): Verifies that the layout geometry adheres to the manufacturing constraints (design rules) specified by the foundry for the target technology node. This includes checks for minimum width, spacing, area, enclosure, overlap, etc., for all layers (metal, poly, diffusion, vias, etc.). Ensures the layout can be physically manufactured with acceptable yield.

LVS (Layout Versus Schematic): Compares GDS(Layout) vs schematic(Netlist). It verifies that the layout correctly implements the intended logic in netlist. It checks, device types, and device parameters (like transistor W/L). Checks for shorts, opens, incorrect connections, missing/extra devices, and parameter mismatches.