Physical Design Interview Guide

oIncorrect Nets / Connectivity Errors: This section details discrepancies in how nets are connected.

Shorts: When Schematic has more nets but layout has less nets, layout has short.

Opens: A single net in the schematic corresponds to two or more unconnected nets in the layout.

Incorrect Instances / Devices: Discrepancies in the number or type of devices.

Missing Devices: A device present in the schematic is not found in the corresponding location/netlist in the layout.

o Fixing IR drop involves 1) strengthening the Power Distribution Network (PDN) to reduce its resistance or 2) reducing the current drawn by the logic.

• During Placement/Floorplan (Preventative)
• Robust PDN Design: Plan a dense power grid using wide straps/rings on low-resistance metal layers with ample vias
• Macro Placement: Place high-power macros near power sources or ensure they have strong connections to the power grid.
• Cell Placement: Avoid clustering high-power or high-switching activity cells in one area. Use density controls.
• During Post-Route Optimization / ECO Stage:
• Strengthen PDN:
• Add/Widen Power Straps: Introduce more power/ground stripes in areas with high voltage drop or increase the width of existing straps.
• Add Power Vias: Increase the number of vias connecting different layers of the power grid, at connections to cell rails, to reduce vertical resistance.
• Add Decap Cells (Primarily for Dynamic IR):
• Reduce Current Draw:
• Cell Downsizing: Replace high-power cells in the violating region with smaller drive-strength equivalents, if no timing violations.
• VT Swapping (Higher Vt): Swap cells to higher-Vt to reduce leakage current (helps static IR) and slightly reduce peak dynamic current (helps dynamic IR), If no timing issues.
• Spread High-Activity Cells: If dynamic IR drop is caused by simultaneously switching cells clustered together, try spreading these cells apart during ECO placement

Crosstalk delay affects timing. This occurs when both the aggressor net and the victim net are switching simultaneously or within a close timing window.

• Opposite Direction Switching: If the aggressor switches in the opposite direction to the victim (e.g., aggressor rises 0->1 while victim falls 1->0), the effect is increased delay on the victim net.
• The aggressor’s transition effectively increases the amount of charge the victim driver needs to supply/remove through the coupling capacitance (Miller effect). This makes the victim’s transition slower.
• Slower transition hurts setup timing but helps hold timing.
• Same Direction Switching: If the aggressor switches in the same direction as the victim (e.g., both rise 0->1), the effect is decreased delay on the victim net.
• The aggressor’s transition helps charge/discharge the coupling capacitance in the same direction the victim driver is trying to go, so speeding up the victim’s transition.
• Faster transition helps setup timing but hurts hold timing. This is often the worst-case scenario for hold analysis.

oIt requires careful analysis and is typically done for critical paths where there is no scope in data path.

• For setup:
• Early the launch clock or delay the capture clock so skew can be increased which helps in setup violation. With this you are reducing the skew in path before and after this path. So there should be setup margin in both adjacent paths and hold margin in same path.
• For Hold:
• Delay the launch clock or early the capture clock so skew can be reduced which helps in hold violations. Path should have setup margin. And path before and after this path should have hold margin as for them it will increase the skew.
• Analyze Clock Path:
• Trace the launch and capture clock paths for the violating timing path.
• Identify existing buffers/inverters on these clock paths, their drive strengths, and locations.
• Understand the common clock path and the diverging points.
• Make desired changes after diverging point, ex, upsize, downsize, add delay based on setup or hold fix.
• Apply ECO in PNR tool and run STA to verify fixes

oLEC (Logical Equivalence Check): Compares Golden netlist or RTL with netlist at any given point in PnR flow to check functionality is same or not.

• Tools like Synopsys Formality or Cadence Conformal are used.
• Non-Equivalent Point: A point (typically a primary output port or a sequential element input/output) in the two designs being compared where the LEC tool has determined that the logic functions driving that point are not equivalent. This indicates a functional difference between the “golden” reference design and the revised/implemented design, meaning the optimization or synthesis process has introduced a functional bug.
• Equivalence Checking Overview: https://www.synopsys.com/glossary/what-is-equivalence-checking.html
• LEC Steps: https://semiconductorclub.com/logic-equivalence-check/

Understanding the Interaction:

• IR Drop -> Setup Violation: Voltage drop (IR drop) at a cell reduces its effective supply voltage, making it slower. This increased cell delay can directly cause or worsen a setup violation.

• Setup Fix -> IR Drop: Some setup fixes, like upsizing cells or swapping to lower Vt, increase the current draw (both peak and average) of those cells. This can worsen IR drop in the local region if the power grid is already marginal.