STA Interview Questions

oFalse Path (set_false_path):

Specific path between a startpoint and endpoint cannot be logically sensitized during normal circuit operation. Although a physical path exists, signals will never actually propagate from the startpoint to the endpoint along that path under functional conditions

STA Action: The tool completely ignores this path for all timing analysis (setup, hold, DRCs). It assumes the path has infinite time to propagate.

When to Use: Only for paths that are guaranteed to be functionally impossible or irrelevant to the timing modes being analyzed.

oDRV – Setup -Hold

• Fixing DEV first can help reduce setup violations as well.
• Usually fix setup first as fixing setup requires touching many cells across timing path. Swapping and sizing on full path based on slack number. This can impact hold violations.
• For hold fix, usually we fix at endpoint, insert buffer or create long route. Touching endpoint has less to no impact on setup hence hold is fixed at last.

oTempus/ PT used for STA.

• PT –
• Size_cell
• Fix_eco_drc
• Fix_eco_timing
• Tempus – eco_opt_desing -dev -setup -hold

oupdate_io_latency not done at block level. This ensures proper clock tree built for IO paths and gives feedback to top level tree so tree is balanced for io paths.

• IO constraints like input_delay and output_delay is assumption. Actual delay might be different and hence misscorelation.
• Different derate factors at top level or OCV variation?
• May introduce additional SI effect during top level

oRecovery time is the minimum amount of time required between the release of an asynchronous signal from the active state to the next active clock edge.

Removal time specifies the minimum amount of time between an active clock edge and the release of an asynchronous control signal.

The following diagram illustrates recovery and removal times for an active low reset signal (RESET_N) and positive-edge triggered CLOCK