STA Interview Questions

o Netlist vs. Layout: LVS clean. If design has shorts, it results in inaccurate extraction for those nets. So LVS clean is preferred.

SPEF File Validity: Check if any issues or critical warning in extraction flow. If there are ignored nets during extraction, paths with those nets will not have accurate timing.

Other consistency chek like Lib and SDC, no missing constraints.

Annotation Check (report_annotated_delay/check): After reading SPEF/SDF, verify that parasitic delays and checks have been successfully annotated onto the design nets and cells. Look for warnings about unannotated elements.

o Register-to-Register (Reg2Reg): Starts at the clock pin of a launch flip-flop/latch and ends at the data input pin (e.g., D) of a capture flip-flop/latch. Both launch and capture elements are controlled by related clocks (often the same clock). This is the most common type of path analyzed for setup/hold within a synchronous design.

Input-to-Register (In2Reg): Starts at a primary input port of the design and ends at the data input pin of a sequential element. Constrained by set_input_delay.

o Netlist:

Timing Libraries (.lib**,** .db**):**

Parasitics Information (SPEF/DSPF/RSPF/SBPF):

Timing Constraints (SDC - Synopsys Design Constraints):

Operating Conditions/MMMC file: Implicitly defined via the library corners selected, but sometimes explicitly set (e.g., specific voltage/temperature for analysis if not tied directly to a library corner).

(Optional) Power Intent (UPF/CPF): If the design has multiple power domains, the UPF/CPF file is needed to understand which supply nets power which cells, enabling power-aware STA.

oOCV analysis (like AOCV/POCV or simple derating) applies different delay values for ’early’ (fast) and ’late’ (slow) conditions.

For a setup check, the launch clock path uses late delays, and the capture clock path uses early delays. For a hold check, it’s reversed.

However, both clock paths often share a common segment starting from the clock root before diverging. Applying both early and late derates simultaneously to this same physical common path introduces artificial pessimism because the common path cannot physically be both fast and slow at the exact same instant.

oMin Pulse Width (MPW) Violation: A timing check ensuring that the duration of a clock pulse (either the high phase or the low phase) at the clock pin of a sequential element (or other sensitive pins like asynchronous resets) is sufficiently long for the cell to function correctly. Libraries specify min_pulse_width_high and min_pulse_width_low requirements. A violation occurs if the actual pulse width reaching the pin is shorter than the required minimum.

oset_case_analysis: particular port or pin in the design should be treated as having a constant logic value (0 or 1) for the duration of the timing analysis run (or for specific modes).

Purpose:

Mode Setting: To model different operating modes of the chip (e.g., functional mode vs. test mode) where certain control signals are tied high or low.

Disabling Logic: By setting control signals (like multiplexer selects, enables) to constant values, specific logic paths can be disabled for timing analysis,