STA Interview Questions

oBuffer/Delay Cell Insertion: Insert buffers or dedicated delay cells into the data path segment between the launch and capture flops.

Cell Sizing (Downsizing): Replace cells on the data path with slower, smaller drive-strength variants (e.g., X4 -> X1). Smaller cells have higher intrinsic delay.

VT Swapping (Higher Vt): Replace cells on the data path with slower, higher-Vt variants (LVT -> SVT -> HVT).

Useful Skew (Negative Skew): Intentionally delay the launch clock path or speed up the capture clock path. Reduce the skew if possible.

oMax_cap vio = the total capacitive load driven by an output pin exceeds the limit specified in the library for that pin. This load includes the input pin capacitance of all driven gates and the capacitance of the interconnect wire. Fixing involves reducing the load seen by the driver or increasing its driving capability:

Buffer Insertion: Insert one or more buffers on the net. Reducing load of longer interconnect.

Driver Cell Sizing (Upsizing): Increase the drive strength of the cell driving the net. Stronger cells are often characterized to handle higher capacitive loads (their max_capacitance limit might be higher).

oSetup Uncertainty = Jitter + skew + Margin

• Hold Uncertainty = Skew + Margin – Jitter will not impact as hold is checked on same edge and no clock period involved in hold check.
• Post CTS we have actual skew hence we reduce uncertainty by that amount.
• Higher the uncertainty, it will reduce that much margin for timing fix, for setup, it reduces required time and hold, it increases required time.
• Crosstalk delay can impact setup and hold. If Aggressor and victim switching in same direction, makes signal faster causing hold violation. And if switching in opposite direction, adds delay causing setup violation.
• Crosstalk noise doesn’t directly impact timing but if glitch is above noise margin, it can be wrongly interpreted as valid switching causing functionality failure

oIf a multicycle path constraint is set with set_multicycle_path 5 -setup, the setup check is performed relative to the active clock edge at the capture flop that occurs 5 clock cycles after the launching clock edge.

Default Setup Check: Edge 1 (relative to launch edge at 0).

MCP 5 Setup Check: Edge 5 (relative to launch edge at 0).

• It’s important to also specify the corresponding hold check using set_multicycle_path 4 -hold to ensure the hold check happens relative to the original launch edge (edge 0), preventing the tool from adding unnecessary delay.

oNO. Even if setup and hold timing checks pass, significant Design Rule Violations (DRVs) either on data or clock needs to be fixed.

Reliability: Slow transitions (max_transition violation) make sequential elements susceptible to noise, glitches, and potential metastability

Timing Accuracy: buffers/inverters are characterized based on expected input transitions and output loads. Violating max_transition or max_capacitance means the library timing models used for setup/hold analysis are inaccurate, invalidating the “clean” timing result. The actual delays might be worse.

oIf setup and hold both are critical on same path, check if it is exact same path or if there is any diversion from combo logic in setup and hold timing path.

If there is any diversion, add delay at that point so hold can be fixed without touching setup critical path.

• If timing path is exactly same and having setup and hold violations, there could be two reasons,
• Crosstalk impact – crosstalk will add delay in setup and reduce it in hold. Impacting adversely both setup and hold. Fixing crosstalk should give margin to fix setup and hold.
• If there is no crosstalk, there can be very high setup and hold time requirement from endpoint. (may happen with reg2mem paths)
• Check if such cells can be replaced with less access time cell.
• To get margin in setup and hold both, you need to use cell with less delay variation across SS-FF corners.
• Use LVT cells in data path instead of SVT/HVT. Use low drive strength cells and reduce net legth so that OCV impact can be reduced giving margin for setup and hold.