STA Interview Questions

oOCV analysis (like AOCV/POCV or simple derating) applies different delay values for ’early’ (fast) and ’late’ (slow) conditions.

For a setup check, the launch clock path uses late delays, and the capture clock path uses early delays. For a hold check, it’s reversed.

However, both clock paths often share a common segment starting from the clock root before diverging. Applying both early and late derates simultaneously to this same physical common path introduces artificial pessimism because the common path cannot physically be both fast and slow at the exact same instant.

oMin Pulse Width (MPW) Violation: A timing check ensuring that the duration of a clock pulse (either the high phase or the low phase) at the clock pin of a sequential element (or other sensitive pins like asynchronous resets) is sufficiently long for the cell to function correctly. Libraries specify min_pulse_width_high and min_pulse_width_low requirements. A violation occurs if the actual pulse width reaching the pin is shorter than the required minimum.

oFalse Path (set_false_path):

Specific path between a startpoint and endpoint cannot be logically sensitized during normal circuit operation. Although a physical path exists, signals will never actually propagate from the startpoint to the endpoint along that path under functional conditions

STA Action: The tool completely ignores this path for all timing analysis (setup, hold, DRCs). It assumes the path has infinite time to propagate.

When to Use: Only for paths that are guaranteed to be functionally impossible or irrelevant to the timing modes being analyzed.